AM79C976 datasheet(133/309 Pages) AMD

133 / 309 page

8/01/00

Am79C976

133

P R E L I M INARY

VAL1

Value bit for byte 1. The value of this bit is written to any bits in the CMD2 register that correspond

to bits in the CMD2[14:8] bit map field that are set to 1.

RCVALGN

Receive Packet Align. When set, this bit forces the data field of ISO 8802-3 (IEEE/ANSI 802.3)

packets to align to 0 MOD 4 address boundaries (i.e., DWord aligned addresses). It is important to

note that this feature will only function correctly if all receive buffer boundaries are DWord aligned

and all receive buffers have 0 MOD 4 lengths. In order to accomplish the data alignment, the

Am79C976 controller simply inserts two bytes of random data at the beginning of the receive

packet (i.e., before the ISO 8802-3 (IEEE/ANSI 802.3) destination address field). The MCNT field

reported to the receive descriptor will not include the extra two bytes.

This bit is an alias of CSR122, bit 0.

ASTRP_RCV

Auto Strip Receive. When set, ASTRP_RCV enables the automatic pad stripping feature. For any

receive frame whose length field has a value less than 46, the pad and FCS fields will be stripped

and not placed in the FIFO.

This bit is an alias of CSR4, bit 10.

FCOLL

Force Collision. This bit allows the collision logic to be tested. The Am79C976 controller must be

in internal loopback for FCOLL to be valid. If FCOLL = 1, a collision will be forced during loopback

transmission attempts, which will result in a Retry Error. If FCOLL = 0, the Force Collision logic will

be disabled.

This bit is an alias of CSR15, bit 4.

EMBA

Enable Modified Back-off Algorithm (see Contention Resolution section in Media Access

Management section for more details). If EMBA is set, a modified back-off algorithm is

implemented.

This bit is an alias of CSR3, bit 3.

DXMT2PD

Disable Transmit Two Part Deferral (see Medium Allocation section in the Media Access

Management section for more details). If DXMT2PD is set, Transmit Two Part Deferral will be

disabled.

This bit is an alias of CSR3, bit 4.

9LTINTEN

Last Transmit Interrupt Enable. When this bit is set to 1, the LTINT bit in transmit descriptors can

be used to determine when transmit interrupts occur. The Transmit Interrupt (TINT) bit will be set

after a frame has been copied to the Transmit FIFO if the LTINT bit in the frame’s last transmit

descriptor is set. If the LTINT bit in the frame’s last descriptor is 0 TINT will not be set after the frame

has been copied to the Transmit FIFO.

This bit is an alias of CSR5, bit 14.

8DXMTFCS

Disable Transmit CRC (FCS). When DXMTFCS is set to 0, the transmitter will generate and append

an FCS to the transmitted frame. When DXMTFCS is set to 1, no FCS is generated or sent with

the transmitted frame. DXMTFCS is overridden when ADD_FCS and ENP bits are set in the

transmit descriptor.

When the auto padding logic, which is enabled by the APAD_XMT bit (CMD2, bit6), adds padding

to a frame, a valid FCS field is appended to the frame, regardless of the state of DXMTFCS.

If DXMTFCS is set and ADD_FCS is clear for a particular frame, no FCS will be generated. If

ADD_FCS is set for a particular frame, the state of DXMTFCS is ignored and a FCS will be

appended on that frame by the transmit circuitry. See also the ADD_FCS bit in the transmit

descriptor.

This bit was called DTCR in the LANCE (Am7990) device.

This bit is an alias of CSR15, bit 3.

7VAL0

Value bit for byte 0. The value of this bit is written to any bits in the CMD2 register that correspond

to bits in the CMD2[6:0] bit map field that are set to 1.

Bit

Name

Description

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