AM79C970A datasheet(145/219 Pages) AMD

145 / 219 page

P R E L I M I N A R Y

AMD

145

Am79C970A

port is active, a value of ONE is

passed to the LEDOUT signal

whenever full-duplex operation

on the GPSI port is enabled

(FDEN

bit

BCR9

set

to ONE).

Read/Write accessible always.

FDLSE is cleared by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

PSE

Pulse Stretcher Enable. When

this bit is set to ONE, the LED illu-

mination time is extended so that

brief occurrences of the enabled

function will be seen on this LED

output. A value of ZERO disables

the pulse stretcher.

Read/Write accessible always.

PSE is set to ONE by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

LNKSTE

Link Status Enable. When this bit

is set to ONE, a value of ONE will

be passed to the LEDOUT bit in

this register when the T-MAU op-

erating in half-duplex mode is in

Link

Pass

state.

When

the

T-MAU operating in half-duplex

mode is in Link Fail state, a value

of ZERO is passed to the

LEDOUT bit.

The function of this bit is masked

if the 10BASE-T port is operating

in full-duplex mode. This allows a

system to have separate LEDs

for half-duplex Link Status and

for full-duplex Link Status.

Read/Write accessible always.

LNKSTE is set to ONE by

H_RESET and is not affected by

S_RESET or by setting the

STOP bit.

RCVME

Receive Match Status Enable.

When this bit is set to ONE, a

value of ONE is passed to the

LEDOUT bit in this register when

the there is receive activity on the

network that has passed the ad-

dress

match

function

for

this node. All address matching

modes are included: physical,

logical

filtering,

broadcast

and promiscuous.

Read/Write accessible always.

RCVME is cleared by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

XMTE

Transmit Status Enable. When

this bit is set to ONE, a value of

ONE is passed to the LEDOUT

bit in this register when there is

transmit activity on the network.

Read/Write accessible always.

XMTE is cleared by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

RXPOLE

Receive Polarity Status Enable.

When this bit is set to ONE, a

value of ONE is passed to the

LEDOUT bit in this register when

the polarity of the RXD

± pair is

not reversed.

Receive polarity indication is

valid only if the T-MAU is in link

pass state.

Read/Write accessible always.

RXPOLE

cleared

H_RESET and is not affected by

S_RESET or by setting the

STOP bit.

RCVE

Receive Status Enable. When

this bit is set to ONE, a value of

ONE is passed to the LEDOUT

bit in this register when there is

receive activity on the network.

Read/Write accessible always.

RCVE is cleared by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

JABE

Jabber status Enable. When

this bit is set to ONE, a value of

ONE is passed to the LEDOUT

bit in this register when the

PCnet-PCI II controller is jabber-

ing on the network.

Read/Write accessible always.

JABE is cleared by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

COLE

Collision status Enable. When

this bit is set to ONE, a value of

ONE is passed to the LEDOUT

bit in this register when there is

collision activity on the network.

The activity on the collision in-

puts to the AUI or GPSI ports

within the first 4

µs after every

transmission for the purpose of

SQE testing will not cause the

LEDOUT bit to be set.

Read/Write accessible always.

COLE is cleared by H_RESET

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