AM79C970A datasheet(218/219 Pages) AMD

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AMD

E-4

Am79C970A

BCR17: I/O Base Address Upper

s This register is no longer programmable through

the EEPROM. The register is reserved and has no

effect on the operation of the device. It is only used

in the PCnet-32.

BCR18: Burst Size and Bus Control

s New bits: ROMTMG (bits 15–12), Expansion ROM

Timing. Was reserved location, read and written as

ZERO.

s New bit: MEMCMD (bit 9), Memory Command.

Was reserved location, read and written as ZERO.

s New bit: EXTREQ (bit 8), Extended Request. Was

reserved location, read and written as ONE.

s BREADE (bit 6), Burst Read Enable. Extended

functionality of bit. Besides enabling burst read

accesses to the transmit buffer, BREADE will now

also enable burst read accesses to the initialization

block and, if SWSTYLE = 3, to the descriptor

ring entries.

s BWRITE (bit 5), Burst Write Enable. Extended

functionality of bit. Besides enabling burst write

accesses to the receive buffer, BWRITE will now

also enable burst write accesses to the descriptor

ring entries, if SWSTYLE = 3.

s LINBC (bits 2–0), Linear Burst Count. These bits

are now reserved and have no effect on the opera-

tion of the device.

BCR20: Software Style

s New bit: APERREN (bit 10), Advanced Parity Error

Handling Enable. Was reserved location, read and

written as ZERO.

s SWSTYLE (bits 7–0), Software Style. New option,

value of THREE selects new PCnet-PCI controller

style that reorders 32-bit descriptor entries to allow

burst accesses.

BCR21: Interrupt Control

s This register is no longer programmable through

the EEPROM. The register is reserved and has no

effect on the operation of the device. It is only used

in the PCnet-32.

BCR22: PCI Latency

s New register. Was reserved location, read and

written as ZERO.

Receive Descriptor

RMD1

s New bit: BPE (bit 23), Bus Parity Error. This bit is

active only if 32-bit software structures are used

for the descriptor ring entries (SWSTYLE = ONE,

TWO or THREE) and if APERREN (BCR20, bit 10)

is set to ONE. Was reserved location, read and

written as ZERO.

s New bit: PAM (bit 22), Physical Address Match.

This bit is active only if 32-bit software structures

are used for the descriptor ring entries (SWSTYLE

= ONE, TWO or THREE). Was reserved location,

read and written as ZERO.

s New bit: LAFM (bit 21), Logical Address Filter

Match. This bit is active only if 32-bit software

structures are used for the descriptor ring entries

(SWSTYLE = ONE, TWO or THREE). Was re-

served location, read and written as ZERO.

s New bit: BAM (bit 20), Broadcast Address Match.

This bit is active only if 32-bit software struc-

tures are used for the descriptor ring entries

(SWSTYLE = ONE, TWO or THREE). Was re-

served location, read and written as ZERO.

Transmit Descriptor

TMD1

s New bit: LTINT (bit 28), Last Transmit Interrupt.

This bit is only active, if LTINTEN (CSR5, bit 14) is

set to ONE. This bit location is shared with the

MORE status bit. The host will write the bit as

LTINT and read it as MORE. The P2 will read the

bit as LTINT and write it as MORE.

s New bit: BPE (bit 23), Bus Parity Error. This bit is

only active, if 32-bit software structures are used

for the descriptor ring entries (SWSTYLE = ONE,

TWO or THREE) and if APERREN (BCR20, bit 10)

is set to ONE. Was reserved location, read and

written as ZERO.

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