AM79C970A datasheet(216/219 Pages) AMD

216 / 219 page

AMD

E-2

Am79C970A

s Pin to disable external transceiver or DC-to-DC

converter. Polarity of assertion state

programmable.

LIST OF REGISTER BIT CHANGES

PCI Configuration Space

Command Register

s ADSTEP (bit 7) now hardwired to ZERO. Was

hardwired to ONE.

s MEMEN (bit 1) now read/write accessible. Was

hardwired to ZERO.

Status Register

s PERR (bit 15) now cleared by H_RESET. Was not

effected by H_RESET.

s SERR (bit 14) now cleared by H_RESET. Was not

effected by H_RESET.

s RMABORT (bit 13) now cleared by H_RESET.

Was not effected by H_RESET.

s RTABORT (bit 12) now cleared by H_RESET. Was

not effected by H_RESET.

s STABORT (bit 11) now cleared by H_RESET. Was

not effected by H_RESET.

s DATAPERR (bit 8) now cleared by H_RESET.

Was not effected by H_RESET.

s FBTBC (bit 7) now hardwired to ONE. Was hard-

wired to ZERO.

Revision ID Register

s This 8-bit register is now hardwired to 1xh. It was

hardwired to 0xh.

Latency Timer Register

s This 8-bit register is now read/write accessible.

Was hardwired to ZERO.

I/O Base Address Register

s IOBASE (bits 31–5) now cleared by H_RESET.

Was not effected by H_RESET.

Memory Mapped I/O Base Address Register

s New 32-bit register. Was reserved, read as ZERO,

writes have no effect.

Expansion ROM Base Address Register

s New 32-bit register. Was reserved, read as ZERO,

writes have no effect.

Interrupt Line Register

s This 8-bit register is now cleared by H_RESET.

Was not effected by H_RESET.

MIN_GNT Register

s New 8-bit register. Was reserved, read as ZERO,

writes have no effect.

MAX_LAT Register

s New 8-bit register. Was reserved, read as ZERO,

writeshave no effect.

Control And Status Registers

CSR0: PCnet-PCI II controller Control and Status

s In addition to the existing interrupt flags, INTR (bit

7), the interrupt summary bit, is also affected by

the new interrupt flags Excessive Deferral Interrupt

(EXDINT), Magic Packet Interrupt (MPINT) Sleep

Interrupt (SLPINT), System Interrupt (SINT) and

User Interrupt (UINT).

CSR3: Interrupt Masks and Deferral

Control

s New bit: DXSUFLO (bit 6), Disable Transmit Stop

on Underflow error. Was reserved location, read

and written as ZERO.

CSR4: Test and Features Control

s New bit: UINTCMD (bit 7), User Interrupt Com-

mand. Was reserved location, read and written

as ZERO.

s New bit: UINT (bit 6), User Interrupt. Was reserved

location, read as ZERO, written as ONE or ZERO.

CSR5:

s New bit: TOKINTD (bit 15), Transmit OK Interrupt

Disable. Was reserved location, read and written

as ZERO.

s New bit: LTINTEN (bit 14), Last Transmit Interrupt

Enable. Was reserved location, read and written as

ZERO.

s New bit: SINT (bit 11), System Interrupt. Was re-

served location, read and written as ZERO.

s New bit: SINTE (bit 10), System Interrupt Enable.

Was reserved location, read and written as ZERO.

s New bit: SLPINT (bit 9), Sleep Interrupt. Was re-

served location, read and written as ZERO.

s New bit: SLPINTE (bit 8), Sleep Interrupt Enable.

Was reserved location, read and written as ZERO.

s New bit: EXDINT (bit 7), Excessive Deferral Inter-

rupt. Was reserved location, read and written as

ZERO.

s New bit: EXDINTE (bit 6), Excessive Deferral Inter-

rupt Enable. Was reserved location, read and writ-

ten as ZERO.

s New bit: MPPLBA (bit 5), Magic Packet Physical

Logical Broadcast Accept. Was reserved location,

read and written as ZERO.

s New bit: MPINT (bit 4), Magic Packet Interrupt.

Was reserved location, read and written as ZERO.

s New bit: MPINTE (bit 3), Magic Packet Interrupt

Enable. Was reserved location, read and written as

ZERO.

s New bit: MPEN (bit 2), Magic Packet Enable. Was

reserved location, read and written as ZERO.

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