AM79C970A datasheet(217/219 Pages) AMD

217 / 219 page

AMD

E-3

Am79C970A

s New bit: MPMODE (bit 1), Magic Packet Mode.

Was reserved location, read and written as ZERO.

s New bit: SPND (bit 0), Suspend. Was reserved

location, read and written as ZERO.

CSR15: Mode

s PORTSEL (bits 8–7), Network Port Select. New

option, value of 10b selects GPSI mode.

CSR58: Software Style

s New bit: APERREN (bit 10), Advanced Parity Error

Handling Enable. Was reserved location, read and

written as ZERO.

s SWSTYLE (bits 7–0), Software Style. New option,

value of THREE selects new PCnet-PCI controller

style that reorders 32-bit descriptor entries to allow

burst accesses.

CSR80: DMA Transfer Counter and FIFO

Threshold Control

s RCVFW (bits 13–12), Receive FIFO Watermark.

Decoding adjusted for the larger FIFO size.

s XMTSP (bits 11–10), Transmit Start Point. Decod-

ing adjusted for the larger FIFO size.

s XMTFW (bits 9–8), Transmit FIFO Watermark. De-

coding adjusted for the larger FIFO size.

s DMATC (bits 7–0), DMA Transfer Count.

Function of the counter is optimized for the PCI

bus environment.

CSR82: Bus Activity Timer

s DMABAT (bits 15–0), DMA Bus Activity Timer.

Function of the counter is optimized for the PCI

bus environment.

CSR88: Chip ID Lower

s New value: 1003h. Was 0003h.

CSR89: Chip ID Upper

s New value : 0262h. Was 0243h.

CSR100: Bus Timeout

s Default value now 0600h (153.6

µs) to adjust to

the larger FIFO size. Default value was 0200h

(51.2

µs).

CSR112: Missed Frame Count

s Counter is stopped while the device is in

suspend mode

Bus Configuration Registers

BCR2: Miscellaneous Configuration

s New bit: INTLEVEL (bit 7), Interrupt Level. Was

reserved location, read and written as ZERO.

s New bit: DXCVRCTL (bit 5), DXCVR Control. Was

reserved location, read and written as ZERO.

s New bit: DXCVRPOL (bit 4), DXCVR Polarity. Was

reserved location, read and written as ZERO.

s New bit: EADISEL (bit 3), EADI Select. Was re-

served location, read and written as ZERO.

BCR4: Link Status LED

s Register is now programmable through

the EEPROM

s New bit: MPSE (bit 9), Magic Packet Status En-

able. Was reserved location, read and written as

ZERO.

s New bit: FDLSE (bit 8), Full Duplex Link Status

Enable. Was reserved location, read and written as

ZERO.

s COLE (bit 0), Collision Status Enable. Corrected

behavior of function. LED will not light up due to

SQE test collision signal.

BCR5: LED1 Status

s Register is now programmable through the

EEPROM

s New bit: MPSE (bit 9), Magic Packet Status En-

able. Was reserved location, read and written as

ZERO.

s New bit: FDLSE (bit 8), Full Duplex Link Status

Enable. Was reserved location, read and written as

ZERO.

s COLE (bit 0), Collision Status Enable. Corrected

behavior of function. LED will not light up due to

SQE test collision signal.

BCR6: LED2 Status

s New register. Was reserved location, the settings

of the register have no effect on the operation of

the device.

BCR7: LED3 Status

s Register is now programmable through

the EEPROM

s New bit: MPSE (bit 9), Magic Packet Status En-

able. Was reserved location, read and written as

ZERO.

s New bit: FDLSE (bit 8), Full Duplex Link Status

Enable. Was reserved location, read and written as

ZERO.

s COLE (bit 0), Collision Status Enable. Corrected

behavior of function. LED will not light up due to

SQE test collision signal.

BCR9: Full Duplex Control

s New register. Was reserved location, read and

written as ZERO.

BCR16: I/O Base Address Lower

s This register is no longer programmable through

the EEPROM. The register is reserved and has no

effect on the operation of the device. It is only used

in the PCnet-32.

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