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DSPIC30F5015 датащи(PDF) 97 Page - Microchip Technology

номер детали DSPIC30F5015
подробное описание детали  High-Performance, 16-Bit Digital Signal Controllers
PDF  236 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

DSPIC30F5015 датащи(HTML) 97 Page - Microchip Technology

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© 2007 Microchip Technology Inc.
DS70135E-page 95
dsPIC30F4011/4012
15.3
Edge-Aligned PWM
Edge-aligned PWM signals are produced by the module
when the PWM time base is in the Free-Running or
Single-Shot mode. For edge-aligned PWM outputs, the
output has a period specified by the value in PTPER
and a duty cycle specified by the appropriate duty cycle
register (see Figure 15-2). The PWM output is driven
active at the beginning of the period (PTMR = 0) and is
driven inactive when the value in the duty cycle register
matches PTMR.
If the value in a particular duty cycle register is zero,
then the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the out-
put on the PWM pin will be active for the entire PWM
period if the value in the duty cycle register is greater
than the value held in the PTPER register.
FIGURE 15-2:
EDGE-ALIGNED PWM
15.4
Center-Aligned PWM
Center-aligned PWM signals are produced by the
module when the PWM time base is configured in a
Continuous Up/Down Count mode (see Figure 15-3).
The PWM compare output is driven to the active state
when the value of the duty cycle register matches the
value of PTMR and the PWM time base is counting
downwards (PTDIR = 1). The PWM compare output is
driven to the inactive state when the PWM time base is
counting upwards (PTDIR = 0) and the value in the
PTMR register matches the duty cycle value.
If the value in a particular duty cycle register is zero,
then the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the out-
put on the PWM pin will be active for the entire PWM
period if the value in the duty cycle register is equal to
the value held in the PTPER register.
FIGURE 15-3:
CENTER-ALIGNED PWM
Period
Duty Cycle
0
PTPER
PTMR
Value
New Duty Cycle Latched
0
PTPER
PTMR
Value
Period
Period/2
Duty
Cycle



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