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DSPIC30F5015 датащи(PDF) 101 Page - Microchip Technology |
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DSPIC30F5015 датащи(HTML) 101 Page - Microchip Technology |
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101 / 236 page ![]() © 2007 Microchip Technology Inc. DS70135E-page 99 dsPIC30F4011/4012 15.11 PWM Output and Polarity Control There are three device Configuration bits associated with the PWM module that provide PWM output pin control: • HPOL Configuration bit • LPOL Configuration bit • PWMPIN Configuration bit These three bits in the FPORBOR Configuration regis- ter (see Section 21.0 “System Integration”) work in conjunction with the six PWM Enable bits (PENxL and PENxH). The Configuration bits and PWM Enable bits ensure that the PWM pins are in the correct states after a device Reset occurs. The PWMPIN Configuration fuse allows the PWM module outputs to be optionally enabled on a device Reset. If PWMPIN = 0, the PWM outputs will be driven to their inactive states at Reset. If PWMPIN = 1 (default), the PWM outputs will be tri- stated. The HPOL bit specifies the polarity for the PWMxH outputs, whereas the LPOL bit specifies the polarity for the PWMxL outputs. 15.11.1 OUTPUT PIN CONTROL The PEN<3:1>H and PEN<3:1>L control bits in the PWMCON1 SFR enable each high PWM output pin and each low PWM output pin, respectively. If a partic- ular PWM output pin is not enabled, it is treated as a general purpose I/O pin. 15.12 PWM Fault Pin There is one Fault pin (FLTA) associated with the PWM module. When asserted, these pins can optionally drive each of the PWM I/O pins to a defined state. 15.12.1 FAULT PIN ENABLE BITS The FLTACON SFR has 3 control bits that determine whether a particular pair of PWM I/O pins is to be controlled by the Fault input pin. To enable a specific PWM I/O pin pair for Fault overrides, the corresponding bit should be set in the FLTACON register. If all enable bits are cleared in the FLTACON register, then the corresponding Fault input pin has no effect on the PWM module and the pin may be used as a general purpose interrupt or I/O pin. 15.12.2 FAULT STATES The FLTACON Special Function Register has 6 bits that determine the state of each PWM I/O pin when it is overridden by a Fault input. When these bits are cleared, the PWM I/O pin is driven to the inactive state. If the bit is set, the PWM I/O pin will be driven to the active state. The active and inactive states are refer- enced to the polarity defined for each PWM I/O pin (HPOL and LPOL polarity control bits). A special case exists when a PWM module I/O pair is in the Complementary mode and both pins are programmed to be active on a Fault condition. The PWMxH pin always has priority in the Complementary mode, so that both I/O pins cannot be driven active simultaneously. 15.12.3 FAULT INPUT MODES The Fault input pin has two modes of operation: • Latched Mode: When the Fault pin is driven low, the PWM outputs will go to the states defined in the FLTACON register. The PWM outputs will remain in this state until the Fault pin is driven high and the corresponding interrupt flag has been cleared in software. When both of these actions have occurred, the PWM outputs will return to normal operation at the beginning of the next PWM cycle or half-cycle boundary. If the interrupt flag is cleared before the Fault condition ends, the PWM module will wait until the Fault pin is no longer asserted to restore the outputs. • Cycle-by-Cycle Mode: When the Fault input pin is driven low, the PWM outputs remain in the defined Fault states for as long as the Fault pin is held low. After the Fault pin is driven high, the PWM outputs return to normal operation at the beginning of the following PWM cycle or half-cycle boundary. The operating mode for the Fault input pin is selected using the FLTAM control bit in the FLTACON Special Function Register. The Fault pin can be controlled manually in software. Note: The Fault pin logic can operate indepen- dent of the PWM logic. If all the enable bits in the FLTACON register are cleared, then the Fault pin could be used as a general purpose interrupt pin. The Fault pin has an interrupt vector, interrupt flag bit and interrupt priority bits associated with it. |
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