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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC12F635ESS датащи(PDF) 189 Page - Microchip Technology |
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PIC12F635ESS датащи(HTML) 189 Page - Microchip Technology |
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189 / 234 page  © 2007 Microchip Technology Inc. DS41232D-page 187 PIC12F635/PIC16F636/639 15.11 AC Characteristics: Analog Front-End for PIC16F639 (Industrial) AC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Supply Voltage 2.0V ≤ VDD ≤ 3.6V Operating temperature -40°C ≤ TAMB ≤ +85°C for industrial LC Signal Input Sinusoidal 300 mVPP Carrier Frequency 125 kHz LCCOM connected to VSS Param No. Sym. Characteristic Min Typ† Max Units Conditions AF01 VSENSE LC Input Sensitivity 13.0 6 mVPP VDD = 3.0V Output enable filter disabled AGCSIG = 0; MODMIN = 00 (33% modulation depth setting) Input = Continuous Wave (CW) Output = Logic level transition from low-to- high at sensitivity level for CW input. AF02 VDE_Q Coil de-Q’ing Voltage - RF Limiter (RFLM) must be active 3— 5 V VDD = 3.0V, Force IIN = 5 μA AF03 RFLM RF Limiter Turn-on Resistance (LCX, LCY, LCZ) — 300 700 Ohm VDD = 2.0V, VIN = 8 VDC AF04 SADJ Sensitivity Reduction — — 0 -30 — — dB dB VDD = 3.0V No sensitivity reduction selected Max reduction selected Monotonic increment in attenuation value from setting = 0000 to 1111 by design AF05 VIN_MOD Minimum Modulation Depth 75% ± 12% 50% ± 12% 25% ± 12% 12% ± 12% 63 38 13 0 75 50 25 12 87 62 37 24 % % % % VDD = 3.0V AF06 CTUNX LCX Tuning Capacitor — 44 0 63 — 82 pF pF VDD = 3.0V, Config. Reg. 1, bits <6:1> Setting = 000000 63 pF +/- 30% Config. Reg. 1, bits <6:1> Setting = 111111 63 steps, 1 pF/step Monotonic increment in capacitor value from setting = 000000 to 111111 by design AF07 CTUNY LCY Tuning Capacitor — 44 0 63 — 82 pF pF VDD = 3.0V, Config. Reg. 2, bits <6:1> Setting = 000000 63 pF +/- 30% Config. Reg. 2, bits <6:1> Setting = 111111 63 steps, 1 pF/step Monotonic increment in capacitor value from setting = 000000 to 111111 by design AF08 CTUNZ LCZ Tuning Capacitor — 44 0 63 — 82 pF pF VDD = 3.0V, Config. Reg. 3, bits<6:1> Setting = 000000 63 pF +/- 30% Config. Reg. 3, bits<6:1> Setting = 111111 63 steps, 1 pF/step Monotonic increment in capacitor value from setting = 000000 to 111111 by design AF09 FCARRIER Carrier frequency — 125 — kHz Characterized at bench. AF10 FMOD Input modulation frequency — — 10 kHz Input data rate, characterized at bench. AF11 C_Q Q of Trimming Capacitors 50* — — pF Characterized at bench test AF12 TDR Demodulator Charge Time (delay time of demodulated output to rise) —50 — μsVDD = 3.0V MOD depth setting = 50% Input conditions: Amplitude = 300 mVPP Modulation depth = 80% AF13 TDF Demodulator Discharge Time (delay time of demodulated output to fall) —50 — μsVDD = 3.0V MOD depth setting = 50% Input conditions: Amplitude = 300 mVPP Modulation depth = 80% * Parameter is characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Required output enable filter high time must account for input path analog delays (= TOEH - TDR + TDF). 2: Required output enable filter low time must account for input path analog delays (= TOEL + TDR - TDF). |
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