Copyright

© ANPEC Electronics Corp.

Rev. A.3 - Sep., 2012

APW8811

www.anpec.com.tw

7

Pin Description

PIN

NO.

NAME

FUNCTION

1

ILIM1

Current-Limit Adjustment. There is an internal 10

µA current source from LDO5 to ILIM1 and connected a

resistor from ILIM1 to GND to set the current-limit threshold. The PGND-PHASE1 current-limit threshold is

1/10

value if ILIM1 is 5V.

2

FB1

Output voltage feedback pin (PWM1). It can use a resistive divider from VOUT1 to GND to adjust the output

from 2V to 5.5V.

3

REF

2V Reference Output. Bypass to GND with a 0.1

µF (minimum) capacitor. REF can supply external loads for

50

µA (maximum). REF load-regulation error will degrade feedback and output accuracy.

4

TON

Frequency Selection Input. Connect to LDO5 for 365kHz(PWM1)/460kHz(PWM2) operation and to LDO3

for 300kHz/375kHz operation. Connect to REF for 245kHz/305kHz operation and to GND for

200kHz/250kHz operation.

5

FB2

Output voltage feedback pin (PWM2). It can use a resistive divider from VOUT2 to GND to adjust the output

from 2V to 5.5V.

6

ILIM2

Current-Limit Adjustment. There is an internal 10

µA current source from LDO5 to ILIM2 and connected a

resistor from ILIM2 to GND to set the current-limit threshold. The PGND-PHASE2 current-limit threshold is

1/10

value if ILIM2 is 5V.

7

VOUT2

PWM2 Output Voltage-Sense Input. The VOUT2 pin makes a direct measurement of the PWM2 output

voltage. VOUT2 is an input to the constant-on-time PWM one-time one-shot circuit.

8

LDO3

3.3V Linear Regulator Output. LDO3 can provide a total of 100mA, 3.3V external loads. When LDO3 is at

3.3V and PWM2 output voltage is over 3.15V bypass threshold, the internal LDO will shut down, and LDO3

output pin connects to VOUT2 through a 1.5

Ω switch. Bypass to GND with a minimum of 2.2µF ceramic

capacitor for stability.

9

BOOT2

Supply Input for The UGATE2 Gate Driver and an internal level-shift circuit. Connect to an external capacitor

to create a boosted voltage suitable to drive a logic-level N-channel MOSFET.

10

UGATE2

Output of The High-Side MOSFET Driver for PWM2. Connect this pin to Gate of the high-side MOSFET.

11

PHASE2

Junction Point of The High-Side MOSFET Source, Output Filter Inductor and The Low-Side MOSFET Drain

for PWM2. Connect this pin to the Source of the high-side MOSFET. PHASE2 serves as the lower supply rail

for the UGATE2 high-side gate driver. PHASE2 is the current-sense input for the PWM2.

12

LGATE2

Output of The Low-Side MOSFET Driver for PWM2. Connect this pin to Gate of the low-side MOSFET.

Swings from PGND to LDO5.

13

EN LDO

Master Enable Input. The LDOx is enabled when EN LDO=1. When ENLDO=0, the LDO is shutdown. See

the table 2 “Power-Up Control Logics.”

14

SKIP#

PWM1 and 2 Controller Operation Mode Control. Connect SKIP# to GND for auto PWM/PFM mode, to REF

for forced-PWM mode and to LDO3 or LDO5 for ultra-sonic mode.

15

PGND

Power Ground of The LGATE Low-Side MOSFET Drivers. Connect the pin to the source of the low-side

MOSFETs.

16

VIN

Battery voltage input pin. VIN powers linear regulators and is also used for the constant-on-time PWM

on-time one-shot circuits. Connect VIN to the battery input and bypass with a 1

µF capacitor for noise

interference.

17

LDO5

5V Linear Regulator Output. LDO5 can provide a total of 100mA, 5V external loads. When LDO5 is at 5V

and PWM1 output voltage is over 4.7V bypass threshold, the internal LDO will shut down, and LDO5 output

pin connects to VOUT1 through a 1.5

Ω switch. Bypass to GND with a minimum of 2.2µF ceramic capacitor

for stability.

18

EN PWM

PWMx Enable Input. Both PWMx are enabled when EN PWM=1. When EN PWM=0, both PWMx are in

shutdown. See the table 2 “Power-Up Control Logics.”

19

LGATE1

Output of The Low-Side MOSFET Driver for PWM1. Connect this pin to Gate of the low-side MOSFET.

Swings from PGND to LDO5.

20

PHASE1

Junction Point of The High-Side MOSFET Source, Output Filter Inductor and The Low-Side MOSFET Drain

for PWM1. Connect this pin to the Source of the high-side MOSFET. PHASE1 serves as the lower supply rail

for the UGATE1 high-side gate driver. PHASE1 is the current-sense input for the PWM1.