Data Sheet

AD5232

Rev. C | Page 5 of 24

INTERFACE TIMING CHARACTERISTICS

Table 2.

Parameter1, 2

Symbol

Conditions

Min

Typ3

Max

Unit

20

ns

CS Setup Time

10

ns

CLK Shutdown Time to CS Rise

1

Input Clock Pulse Width

Clock level high or low

10

ns

Data Setup Time

From positive CLK transition

5

ns

Data Hold Time

From positive CLK transition

5

ns

CS to SDO-SPI Line Acquire

40

ns

CS to SDO-SPI Line Release

50

ns

CLK to SDO Propagation Delay4

50

ns

CLK to SDO Data Hold Time

0

ns

CS High Pulse Width5

10

ns

CS High to CS High5

4

RDY Rise to CS Fall

0

ns

CS Rise to RDY Fall Time

0.15

0.3

ms

Store/Read EEMEM Time6

Applies to Command Instruction 2, Command

Instruction 3, and Command Instruction 9

25

ms

CS Rise to Clock Rise/Fall Setup

10

ns

Preset Pulse Width (Asynchronous)

Not shown in timing diagram

50

ns

Preset Response Time to RDY High

PR pulsed low to refresh wiper positions

70

µs

1

Guaranteed by design; not subject to production test.

2

See the Timing Diagrams section for the location of measured values.

3

4

5

Valid for commands that do not activate the RDY pin.

6

RDY pin low only for Command Instruction 2, Command Instruction 3, Command Instruction 8, Command Instruction 9, Command Instruction 10, and the PR hardware pulse: