AT90USB646 datasheet(47/456 Pages) ATMEL

47 / 456 page

7593L–AVR–09/12

AT90USB64/128

Note that the System Clock Prescaler can be used to implement run-time changes of the internal

clock frequency while still ensuring stable operation. Refer to “System clock prescaler” on page

47 for details.

7.7

Clock output buffer

The device can output the system clock on the CLKO pin. To enable the output, the CKOUT

Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-

cuits on the system. The clock also will be output during reset, and the normal operation of I/O

pin will be overridden when the fuse is programmed. Any clock source, including the internal RC

Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is

used, it is the divided system clock that is output.

7.8

Timer/counter oscillator

The device can operate its Timer/Counter2 from an external 32.768kHz watch crystal or a exter-

nal clock source. See Figure 7-2 on page 43 for crystal connection.

Applying an external clock source to TOSC1 requires EXCLK in the ASSR Register written to

logic one. See “Asynchronous operation of the Timer/Counter” on page 161 for further descrip-

tion on selecting external clock as input instead of a 32kHz crystal.

7.9

System clock prescaler

The Atmel AT90USB64/128 has a system clock prescaler, and the system clock can be divided

by setting the “CLKPR – Clock Prescale Register” on page 48. This feature can be used to

decrease the system clock frequency and the power consumption when the requirement for pro-

cessing power is low. This can be used with all clock source options, and it will affect the clock

frequency of the CPU and all synchronous peripherals. clk

I/O, clkADC, clkCPU, and clkFLASH are

divided by a factor as shown in Table 7-10 on page 48.

When switching between prescaler settings, the System Clock Prescaler ensures that no

glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than

neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-

sponding to the new setting.

The ripple counter that implements the prescaler runs at the frequency of the undivided clock,

which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the

state of the prescaler - even if it were readable, and the exact time it takes to switch from one

clock division to the other cannot be exactly predicted. From the time the CLKPS values are writ-

ten, it takes between T1 + T2 and T1 + 2 × T2 before the new clock frequency is active. In this

interval, two active clock edges are produced. Here, T1 is the previous clock period, and T2 is

the period corresponding to the new prescaler setting.

To avoid unintentional changes of clock frequency, a special write procedure must be followed

to change the CLKPS bits:

Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in

CLKPR to zero.

Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure the write procedure is

not interrupted.

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