AT90USB646 datasheet(33/456 Pages) ATMEL

33 / 456 page

7593L–AVR–09/12

AT90USB64/128

6.5.4

Pull-up and bus-keeper

The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to

one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by

writing the Port register to zero before entering sleep.

The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper can be dis-

abled and enabled in software as described in “XMCRB – External Memory Control Register B”

on page 36. When enabled, the bus-keeper will keep the previous value on the AD7:0 bus while

these lines are tri-stated by the XMEM interface.

6.5.5

Timing

External Memory devices have different timing requirements. To meet these requirements, the

XMEM interface provides four different wait-states as shown in Table 6-5 on page 36. It is impor-

tant to consider the timing specification of the External Memory device before selecting the wait-

state. The most important parameters are the access time for the external memory compared to

the setup requirement. The access time for the External Memory is defined to be the time from

receiving the chip select/address until the data of this address actually is driven on the bus. The

access time cannot exceed the time from the ALE pulse must be asserted low until data is stable

during a read sequence (see t

LLRL+ tRLRH - tDVRH in Tables 31-6 through Tables 31-13 on pages

399 - 401). The different wait-states are set up in software. As an additional feature, it is possible

to divide the external memory space in two sectors with individual wait-state settings. This

makes it possible to connect two different memory devices with different timing requirements to

the same XMEM interface. For XMEM interface timing details, please refer to Tables 31-6

through Tables 31-13 and Figure 31-7 to Figure 31-10 in the “External data memory timing” on

page 399.

Note that the XMEM interface is asynchronous and that the waveforms in the following figures

are related to the internal system clock. The skew between the internal and external clock

(XTAL1) is not guarantied (varies between devices temperature, and supply voltage). Conse-

quently, the XMEM interface is not suited for synchronous operation.

Figure 6-6.

External data memory cycles without wait-state (SRWn1=0 and SRWn0=0).

ALE

A15:8

Address

Prev. addr.

DA7:0

Address

Data

Prev. data

DA7:0 (XMBK = 0)

Data

Prev. data

Address

Data

Prev. data

Address

DA7:0 (XMBK = 1)

System Clock (CLKCPU)

AT90USB646 датащи(PDF) 33 Page - ATMEL Corporation

AT90USB646 датащи(HTML) 33 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL