DSPIC30F5015 datasheet(101/234 Pages) MICROCHIP

101 / 234 page

DS70149E-page 101

dsPIC30F5015/5016

FIGURE 15-2:

EDGE-ALIGNED PWM

15.4

Center-Aligned PWM

Center-aligned PWM signals are produced by the

module when the PWM time base is configured in an

Up/Down Counting mode (see Figure 15-3).

The PWM compare output is driven to the active state

when the value of the Duty Cycle register matches the

value of PTMR and the PWM time base is counting

downwards (PTDIR = 1). The PWM compare output is

driven to the inactive state when the PWM time base is

counting upwards (PTDIR = 0) and the value in the

PTMR register matches the duty cycle value.

If the value in a particular Duty Cycle register is zero,

then the output on the corresponding PWM pin will be

inactive for the entire PWM period. In addition, the out-

put on the PWM pin will be active for the entire PWM

period if the value in the Duty Cycle register is equal to

the value held in the PTPER register.

FIGURE 15-3:

CENTER-ALIGNED PWM

15.5

PWM Duty Cycle Comparison

Units

There are four 16-bit Special Function Registers

(PDC1, PDC2, PDC3 and PDC4) used to specify duty

cycle values for the PWM module.

The value in each Duty Cycle register determines the

amount of time that the PWM output is in the active

state. The Duty Cycle registers are 16 bits wide. The

LSb of a Duty Cycle register determines whether the

PWM edge occurs in the beginning. Thus, the PWM

resolution is effectively doubled.

Period

Duty Cycle

PTPER

PTMR

Value

New Duty Cycle Latched

PTPER

PTMR

Value

Period

Period/2

Duty

Cycle

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