DSPIC30F5015 datasheet(68/234 Pages) MICROCHIP

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dsPIC30F5015/5016

DS70149E-page 68

FIGURE 9-1:

16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER)

9.1

Timer Gate Operation

The 16-bit timer can be placed in the Gated Time

Accumulation mode. This mode allows the internal TCY

to increment the respective timer when the gate input

signal (T1CK pin) is asserted high. Control bit TGATE

(T1CON<6>) must be set to enable this mode. The

timer must be enabled (TON = 1) and the timer clock

source set to internal (TCS = 0).

When the CPU goes into the Idle mode, the timer will

stop incrementing unless TSIDL = 0. If TSIDL = 1, the

timer will resume the incrementing sequence upon

termination of the CPU Idle mode.

9.2

Timer Prescaler

The input clock (FOSC/4 or external clock) to the 16-bit

timer has a prescale option of 1:1, 1:8, 1:64 and 1:256,

selected by control bits, TCKPS<1:0> (T1CON<5:4>).

The prescaler counter is cleared when any of the

following occurs:

• A write to the TMR1 register

• Clearing the TON bit (T1CON<15>)

• A device Reset, such as POR and BOR

However, if the timer is disabled (TON = 0), then the

timer prescaler cannot be reset since the prescaler

clock is halted.

TMR1 is not cleared when T1CON is written. It is

cleared by writing to the TMR1 register.

9.3

Timer Operation During Sleep

Mode

During CPU Sleep mode, the timer will operate if:

• The timer module is enabled (TON = 1) and

• The timer clock source is selected as external

(TCS = 1) and

• The TSYNC bit (T1CON<2>) is asserted to a logic

‘0’, which defines the external clock source as

asynchronous

When all three conditions are true, the timer will con-

tinue to count up to the Period register and be reset to

0x0000.

When a match between the timer and the Period regis-

ter occurs, an interrupt can be generated, if the

respective timer interrupt enable bit is asserted.

TON

Sync

SOSCI

SOSCO/

PR1

T1IF

Equal

Comparator x 16

TMR1

Reset

LPOSCEN

Event Flag

TSYNC

TGATE

TCKPS<1:0>

Prescaler

1, 8, 64, 256

TGATE

TCY

T1CK

1 x

0 1

0 0

Gate

Sync

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