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DSPIC33FJ12GP201TE/ML датащи(PDF) 4 Page - Microchip Technology |
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DSPIC33FJ12GP201TE/ML датащи(HTML) 4 Page - Microchip Technology |
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4 / 242 page ![]() dsPIC33FJ12GP201/202 DS70264B-page 2 Preliminary © 2007 Microchip Technology Inc. Communication Modules: • 4-wire SPI: - Framing supports I/O interface to simple codecs - Supports 8-bit and 16-bit data - Supports all serial clock formats and sampling modes •I2C™: - Full Multi-Master Slave mode support - 7-bit and 10-bit addressing - Bus collision detection and arbitration - Integrated signal conditioning - Slave address masking •UART: - Interrupt on address bit detect - Interrupt on UART error - Wake-up on Start bit from Sleep mode - 4 character TX and RX FIFO buffers - LIN bus support -IrDA® encoding and decoding in hardware - High-Speed Baud mode - Hardware Flow Control with CTS and RTS Analog-to-Digital Converters (ADCs): • 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion: - 2 and 4 simultaneous samples (10-bit ADC) - Up to 10 input channels with auto-scanning - Conversion start can be manual or synchronized with 1 of 4 trigger sources - Conversion possible in Sleep mode - ±2 LSb max integral nonlinearity - ±1 LSb max differential nonlinearity CMOS Flash Technology: • Low-power, high-speed Flash technology • Fully static design • 3.3V (±10%) operating voltage • Industrial and extended temperature • Low power consumption Packaging: • 18-pin SDIP/SOIC • 28-pin SDIP/SOIC/QFN Note: See the device variant tables for exact peripheral features per device. |
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