DSPIC33FJ12GP201TESLASHML datasheet(27/242 Pages) MICROCHIP

27 / 242 page

Preliminary

DS70264B-page 25

dsPIC33FJ12GP201/202

3.2

Data Address Space

The dsPIC33FJ12GP201/202 CPU has a separate

16-bit-wide data memory space. The data space is

accessed using separate Address Generation Units

(AGUs) for read and write operations. The data

memory maps is shown in Figure 3-3.

All Effective Addresses (EAs) in the data memory space

are 16 bits wide and point to bytes within the data space.

This arrangement gives a data space address range of

64 Kbytes or 32K words. The lower half of the data

memory space (that is, when EA<15> = 0) is used for

implemented memory addresses, while the upper half

(EA<15> = 1) is reserved for the Program Space

Visibility area (see Section 3.6.3 “Reading Data From

Program Memory Using Program Space Visibility”).

dsPIC33FJ12GP201/202 devices implement up to

30 Kbytes of data memory. Should an EA point to a

location outside of this area, an all-zero word or byte

will be returned.

3.2.1

DATA SPACE WIDTH

The data memory space is organized in byte address-

able, 16-bit-wide blocks. Data is aligned in data

memory and registers as 16-bit words, but all data

space EAs resolve to bytes. The Least Significant

Bytes (LSBs) of each word have even addresses, while

the Most Significant Bytes (MSBs) have odd

addresses.

3.2.2

DATA MEMORY ORGANIZATION

AND ALIGNMENT

To maintain backward compatibility with PIC® MCU

devices and improve data space memory usage

efficiency, the dsPIC33FJ12GP201/202 instruction set

supports both word and byte operations. As a conse-

quence of byte accessibility, all effective address calcu-

lations are

internally scaled to step through

word-aligned memory. For example, the core recog-

nizes that Post-Modified Register Indirect Addressing

mode [Ws++] will result in a value of Ws + 1 for byte

operations and Ws + 2 for word operations.

Data byte reads will read the complete word that

contains the byte, using the LSB of any EA to

determine which byte to select. The selected byte is

placed onto the LSB of the data path. That is, data

memory and registers are organized as two parallel

byte-wide entities with shared (word) address decode

but separate write lines. Data byte writes only write to

the corresponding side of the array or register that

matches the byte address.

All word accesses must be aligned to an even address.

Misaligned word data fetches are not supported, so

care must be taken when mixing byte and word opera-

tions, or translating from 8-bit MCU code. If a mis-

aligned read or write is attempted, an address error

trap is generated. If the error occurred on a read, the

instruction underway is completed. If the instruction

occurred on a write, the instruction is executed but the

write does not occur. In either case, a trap is then exe-

cuted, allowing the system and/or user application to

examine the machine state prior to execution of the

address Fault.

All byte loads into any W register are loaded into the

Least Significant Byte. The Most Significant Byte is not

modified.

A sign-extend instruction (SE) is provided to allow

users to translate 8-bit signed data to 16-bit signed

values. Alternatively, for 16-bit unsigned data, user

applications can clear the MSB of any W register by

executing a zero-extend (ZE) instruction on the

appropriate address.

3.2.3

SFR SPACE

The first 2 Kbytes of the near data space, from 0x0000

to 0x07FF, is primarily occupied by Special Function

Registers

(SFRs).

These

are

used

the

dsPIC33FJ12GP201/202 core and peripheral modules

for controlling the operation of the device.

SFRs are distributed among the modules that they

control, and are generally grouped together by module.

Much of the SFR space contains unused addresses;

these are read as ‘0’. A complete listing of implemented

SFRs, including their addresses, is shown in Table 3-1

through Table 3-21.

3.2.4

NEAR DATA SPACE

The 8-Kbyte area between 0x0000 and 0x1FFF is

referred to as the near data space. Locations in this

space are directly addressable via a 13-bit absolute

address field within all memory direct instructions.

Additionally, the whole data space is addressable using

MOV instructions, which support Memory Direct

Addressing mode with a 16-bit address field, or by

using Indirect Addressing mode using a working

Note:

The actual set of peripheral features and

interrupts varies by the device. Refer to

the corresponding device tables and

pinout diagrams for device-specific

information.

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