48GA004 datasheet(109/268 Pages) MICROCHIP

109 / 268 page

 2010 Microchip Technology Inc.

DS39881D-page 109

PIC24FJ64GA004 FAMILY

TABLE 10-3:

SELECTABLE OUTPUT

SOURCES (MAPS FUNCTION

TO OUTPUT)

10.4.3.3

Mapping Limitations

The control schema of the peripheral pin select is

extremely flexible. Other than systematic blocks that

prevent signal contention caused by two physical pins

being configured as the same functional input or two

functional outputs configured as the same pin, there

are no hardware enforced lock outs. The flexibility

extends to the point of allowing a single input to drive

multiple peripherals or a single functional output to

drive multiple output pins.

10.4.4

CONTROLLING CONFIGURATION

CHANGES

Because peripheral remapping can be changed during

run time, some restrictions on peripheral remapping

are needed to prevent accidental configuration

changes. PIC24F devices include three features to

prevent alterations to the peripheral map:

• Control register lock sequence

• Continuous state monitoring

• Configuration bit remapping lock

10.4.4.1

Control Register Lock

Under normal operation, writes to the RPINRx and

RPORx registers are not allowed. Attempted writes will

appear to execute normally, but the contents of the

registers will remain unchanged. To change these reg-

isters, they must be unlocked in hardware. The register

lock is controlled by the IOLOCK bit (OSCCON<6>).

Setting IOLOCK prevents writes to the control

registers; clearing IOLOCK allows writes.

To set or clear IOLOCK, a specific command sequence

must be executed:

Write 46h to OSCCON<7:0>.

Write 57h to OSCCON<7:0>.

Clear (or set) IOLOCK as a single operation.

Unlike the similar sequence with the oscillator’s LOCK

bit, IOLOCK remains in one state until changed. This

allows all of the peripheral pin selects to be configured

with a single unlock sequence followed by an update to

all control registers, then locked with a second lock

sequence.

10.4.4.2

Continuous State Monitoring

In addition to being protected from direct writes, the

contents of the RPINRx and RPORx registers are

constantly monitored in hardware by shadow registers.

If an unexpected change in any of the registers occurs

(such as cell disturbances caused by ESD or other

external events), a Configuration Mismatch Reset will

be triggered.

10.4.4.3

Configuration Bit Pin Select Lock

As an additional level of safety, the device can be con-

figured to prevent more than one write session to the

RPINRx and RPORx registers. The IOL1WAY

(CW2<4>) Configuration bit blocks the IOLOCK bit

from being cleared after it has been set once. If

IOLOCK remains set, the register unlock procedure will

not execute and the Peripheral Pin Select Control reg-

isters cannot be written to. The only way to clear the bit

and re-enable peripheral remapping is to perform a

device Reset.

In the default (unprogrammed) state, IOL1WAY is set,

restricting users to one write session. Programming

IOL1WAY allows users unlimited access (with the

proper use of the unlock sequence) to the Peripheral

Pin Select registers.

Function

Output Function

Number(1)

Output Name

NULL(2)

NULL

C1OUT

Comparator 1 Output

C2OUT

Comparator 2 Output

U1TX

UART1 Transmit

U1RTS(3)

UART1 Request To Send

U2TX

UART2 Transmit

U2RTS(3)

UART2 Request To Send

SDO1

SPI1 Data Output

SCK1OUT

SPI1 Clock Output

SS1OUT

SPI1 Slave Select Output

SDO2

SPI2 Data Output

SCK2OUT

SPI2 Clock Output

SS2OUT

SPI2 Slave Select Output

OC1

Output Compare 1

OC2

Output Compare 2

OC3

Output Compare 3

OC4

Output Compare 4

OC5

Output Compare 5

Note 1:

Value assigned to the RPn<4:0> pins corre-

sponds to the peripheral output function

number.

The NULL function is assigned to all RPn

outputs at device Reset and disables the

RPn output function.

IrDA® BCLK functionality uses this output.

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