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48GA004 датащи(PDF) 12 Page - Microchip Technology |
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48GA004 датащи(HTML) 12 Page - Microchip Technology |
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12 / 268 page ![]() PIC24FJ64GA004 FAMILY DS39881D-page 12 2010 Microchip Technology Inc. FIGURE 1-1: PIC24FJ64GA004 FAMILY GENERAL BLOCK DIAGRAM Instruction Decode & Control 16 PCH PCL 16 Program Counter 16-Bit ALU 23 24 Data Bus Inst Register 16 Divide Support Inst Latch 16 EA MUX Read AGU Write AGU 16 16 8 Interrupt Controller PSV & Table Data Access Control Block Stack Control Logic Repeat Control Logic Data Latch Data RAM Address Latch Address Latch Program Memory Data Latch 16 Address Bus 23 Control Signals 16 16 16 x 16 W Reg Array Multiplier 17x17 OSCI/CLKI OSCO/CLKO VDD, Timing Generation VSS MCLR Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer BOR and Precision Reference Band Gap FRC/LPRC Oscillators Regulator Voltage VDDCORE/VCAP DISVREG PORTA(1) PORTC(1) RA0:RA9 RC0:RC9 PORTB RB0:RB15 Note 1: Not all pins or features are implemented on all device pinout configurations. See Table 1-2 for I/O port pin descriptions. 2: BOR and LVD functionality is provided when the on-board voltage regulator is enabled. 3: Peripheral I/Os are accessible through remappable pins. RP(1) RP0:RP25 Comparators(3) Timer2/3(3) Timer1 RTCC IC1-5(3) ADC 10-Bit PWM/ SPI1/2(3) I2C1/2 Timer4/5(3) PMP/PSP OC1-5(3) CN1-22(1) UART1/2(3) LVD(2) |
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