48GA004 datasheet(98/268 Pages) MICROCHIP

98 / 268 page

PIC24FJ64GA004 FAMILY

DS39881D-page 98

 2010 Microchip Technology Inc.

bit 7

CLKLOCK:

Clock Selection Lock Enabled bit

If FSCM is enabled (FCKSM1 = 1):

= Clock and PLL selections are locked

= Clock and PLL selections are not locked and may be modified by setting the OSWEN bit

If FSCM is disabled (FCKSM1 = 0):

Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.

bit 6

IOLOCK:

I/O Lock Enable bit(2)

= I/O lock is active

= I/O lock is not active

bit 5

LOCK:

PLL Lock Status bit(3)

= PLL module is in lock or PLL module start-up timer is satisfied

= PLL module is out of lock, PLL start-up timer is running or PLL is disabled

bit 4

Unimplemented:

Read as ‘0’

bit 3

CF:

Clock Fail Detect bit

= FSCM has detected a clock failure

= No clock failure has been detected

bit 2

Unimplemented:

Read as ‘0’

bit 1

SOSCEN:

32 kHz Secondary Oscillator (SOSC) Enable bit

= Enable secondary oscillator

= Disable secondary oscillator

bit 0

OSWEN:

Oscillator Switch Enable bit

= Initiate an oscillator switch to clock source specified by NOSC2:NOSC0 bits

= Oscillator switch is complete

OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)

Note 1:

Reset values for these bits are determined by the FNOSC Configuration bits.

The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In

addition, if the IOL1WAY Configuration bit is ‘1’ once the IOLOCK bit is set, it cannot be cleared.

Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.

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