48GA004 datasheet(33/268 Pages) MICROCHIP

33 / 268 page

 2010 Microchip Technology Inc.

DS39881D-page 33

PIC24FJ64GA004 FAMILY

4.2

Data Address Space

The PIC24F core has a separate, 16-bit wide data mem-

ory space, addressable as a single linear range. The

data space is accessed using two Address Generation

Units (AGUs), one each for read and write operations.

The data space memory map is shown in Figure 4-3.

All Effective Addresses (EAs) in the data memory space

are 16 bits wide and point to bytes within the data space.

This gives a data space address range of 64 Kbytes or

32K words. The lower half of the data memory space

(that is, when EA<15> = 0) is used for implemented

memory addresses, while the upper half (EA<15> = 1) is

reserved for the program space visibility area (see

Section 4.3.3 “Reading Data From Program Memory

Using Program Space Visibility”

PIC24FJ64GA family devices implement a total of

8 Kbytes of data memory. Should an EA point to a

location outside of this area, an all zero word or byte will

be returned.

4.2.1

DATA SPACE WIDTH

The

data

memory

space

organized

byte-addressable, 16-bit wide blocks. Data is aligned

in data memory and registers as 16-bit words, but all

data space EAs resolve to bytes. The Least Significant

Bytes of each word have even addresses, while the

Most Significant Bytes have odd addresses.

FIGURE 4-3:

DATA SPACE MEMORY MAP FOR PIC24FJ64GA004 FAMILY DEVICES(1)

0000h

07FEh

FFFEh

LSB

Address

LSB

MSB

Address

0001h

07FFh

1FFFh

FFFFh

8001h

8000h

7FFFh

0801h

0800h

2001h

Near

1FFEh

SFR

SFR Space

Data RAM

2000h

7FFFh

Program Space

Visibility Area

Note 1:

Data memory areas are not shown to scale.

Upper memory limit for PIC24FJ16GAXXX devices is 17FFh.

27FEh(2)

2800h

27FFh(2)

2801h

Space

Data Space

Implemented

Data RAM

Unimplemented

Read as ‘0’

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