48GA004 datasheet(107/268 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS39881D-page 107

PIC24FJ64GA004 FAMILY

10.4

Peripheral Pin Select

A major challenge in general purpose devices is provid-

ing the largest possible set of peripheral features while

minimizing the conflict of features on I/O pins. The chal-

lenge is even greater on low pin count devices similar

to the PIC24FJ64GA family. In an application that

needs to use more than one peripheral multiplexed on

single pin, inconvenient workarounds in application

code or a complete redesign may be the only option.

The peripheral pin select feature provides an alterna-

tive to these choices by enabling the user’s peripheral

set selection and their placement on a wide range of

I/O pins. By increasing the pinout options available on

a particular device, users can better tailor the

microcontroller to their entire application, rather than

trimming the application to fit the device.

The peripheral pin select feature operates over a fixed

subset of digital I/O pins. Users may independently

map the input and/or output of any one of many digital

peripherals to any one of these I/O pins. Peripheral pin

select is performed in software and generally does not

require the device to be reprogrammed. Hardware

safeguards are included that prevent accidental or

spurious changes to the peripheral mapping once it has

been established.

10.4.1

AVAILABLE PINS

The peripheral pin select feature is used with a range

of up to 26 pins; the number of available pins is depen-

dent on the particular device and its pincount. Pins that

support the peripheral pin select feature include the

designation “RPn” in their full pin designation, where

“RP” designates a remappable peripheral and “n” is the

remappable pin number. See Table 1-2 for pinout

options in Each Package Offering.

10.4.2

AVAILABLE PERIPHERALS

The peripherals managed by the peripheral pin select

are all digital only peripherals. These include general

serial communications (UART and SPI), general pur-

pose timer clock inputs, timer related peripherals (input

capture and output compare) and external interrupt

inputs. Also included are the outputs of the comparator

module, since these are discrete digital signals.

The peripheral pin select module is not applied to

I2C™, change notification inputs, RTCC alarm outputs

or peripherals with analog inputs.

A key difference between pin select and non pin select

peripherals is that pin select peripherals are not asso-

ciated with a default I/O pin. The peripheral must

always be assigned to a specific I/O pin before it can be

used. In contrast, non pin select peripherals are always

available on a default pin, assuming that the peripheral

is active and not conflicting with another peripheral.

10.4.2.1

Peripheral Pin Select Function

Priority

When a pin selectable peripheral is active on a given

I/O pin, it takes priority over all other digital I/O and dig-

ital communication peripherals associated with the pin.

Priority is given regardless of the type of peripheral that

is mapped. Pin select peripherals never take priority

over any analog functions associated with the pin.

10.4.3

CONTROLLING PERIPHERAL PIN

SELECT

Peripheral pin select features are controlled through

two sets of Special Function Registers: one to map

peripheral inputs, and one to map outputs. Because

they are separately controlled, a particular peripheral’s

input and output (if the peripheral has both) can be

placed on any selectable function pin without

constraint.

The association of a peripheral to a peripheral select-

able pin is handled in two different ways, depending on

if an input or an output is being mapped.

10.4.3.1

Input Mapping

The inputs of the peripheral pin select options are

mapped on the basis of the peripheral; that is, a control

will be mapped to. The RPINRx registers are used to

configure peripheral input mapping (see Register 10-1

through Register 10-14). Each register contains two

sets of 5-bit fields, with each set associated with one of

the pin selectable peripherals. Programming a given

peripheral’s bit field with an appropriate 5-bit value

maps the RPn pin with that value to that peripheral. For

any given device, the valid range of values for any of

the bit fields corresponds to the maximum number of

peripheral pin selections supported by the device.

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