AM3703CUS datasheet(228/280 Pages) TI

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mcspi_cs(OUT)

mcspi_clk(OUT)

mcspi_simo(OUT)

mcspi_cs(OUT)

mcspi_clk(OUT)

mcspi_simo(OUT)

Bit n–1

Bit n–2

Bit n–3

Bit n–4

Bit 0

Bit n–1

Bit n–2

Bit n–3

Bit 1

Bit 0

PHA=0

EPOL=1

POL=0

POL=1

PHA=1

EPOL=1

POL=0

POL=1

SM5

SM6

SM4

SM1

SM0

SM1

SM0

SM5

SM6

SM1

SM0

SM1

SM0

SM4

SM7

SM4

SM1

SM4

SWPS038-072

AM3715, AM3703

SPRS616F

– JUNE 2010 – REVISED AUGUST 2011

www.ti.com

(1) In mcspi3_csn, n is equal to 0 or 1. The polarity of mcspi3_clk and the active edge (rising or falling) on which mcspi3_simo is driven and

mcspi3_somi is latched is all software configurable.

–

mcspi3_clk phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 1 (Modes 1 and 3).

–

mcspi3_clk phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 0 (Modes 0 and 2).

For more information, see the McSPI environment chapter, Data Format Configurations section of the AM/DM37x Multimedia Device

Technical Reference Manual (literature number SPRUGN4) for modes and phase correspondence description.

(2) This timing applies to all configurations regardless of McSPI3_CLK polarity and which clock edges are used to drive output data and

capture input data.

(3) P = mcspi3_clk clock period

(4) Case P = 20.8 ns, A = (TCS + 0.5)*P(3) (TCS is a bit field of MSPI_CHCONFx[26:25] register).

Case P

> 20.8 ns, A = TCS*P(3) (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of

AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).

(5) B = TCS*P(3) (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of AM/DM37x

Multimedia Device Technical Reference Manual (literature number SPRUGN4).

(6) See Section 4.3.4, Processor Clocks.

(1)

The active clock edge selection of mcspi_clk (rising or falling) on which mcspi_simo is driven and mcspi_somi data is latched is

software configurable with the bit MCSPI_CH(i)CONF[1] = POL and the bit MCSPI_CH(i)CONF[0] = PHA.

(2)

The polarity of mcspi_ncs is software configuable with the bit MCSPI_CH(i)CONF[6] = EPOL.

Figure 6-46. McSPI

—Master Mode—Transmit

228

Timing Requirements and Switching Characteristics

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