AM3703CUS datasheet(227/280 Pages) TI

227 / 280 page

AM3715, AM3703

www.ti.com

SPRS616F

– JUNE 2010 – REVISED AUGUST 2011

(1) In mcspix, x is equal to 1, 2, or 4. In mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 4.

(2) The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all

software configurable:

–

mcspix_clk(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 1 (Modes 1 and 3).

–

mcspix_clk(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 0 (Modes 0 and 2).

For more information, see the McSPI environment chapter, Data Format Configurations section of the AM/DM37x Multimedia Device

Technical Reference Manual (literature number SPRUGN4) for modes and phase correspondence description.

(3) P = mcspix_clk clock period

(4) Case P = 20.8 ns, A = (TCS+0.5)*P(3) (TCS is a bit field of MSPI_CHCONFx[26:25] register).

Case P

> 20.8 ns, A = TCS*P(3) (TCS is a bitfield of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of

the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).

(5) B = TCS*P(3) (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of the AM/DM37x

Multimedia Device Technical Reference Manual (literature number SPRUGN4).

(6) See Section 4.3.4, Processor Clocks.

Table 6-80. McSPI3 Timing Requirements

—Master Mode(1)

NO.

PARAMETER

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

SM2

tsu(SOMIV-CLKAE) Setup time, mcspi3_somi valid before mcspi3_clk

1.5

4.3

active edge

SM3

th(SOMIV-CLKAE)

Hold time, mcspi3_somi valid after mcspi3_clk active

2.8

5.9

edge

(1) See Section 4.3.4, Processor Clocks.

Table 6-81. McSPI3 Switching Characteristics

—Master Mode(1) (2) (6)

NO.

PARAMETER

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

SM0

1/tc(CLK)

Frequency, mcspi3_clk

MHz

SM1

tw(CLKH)

Pulse duration, mcspi3_clk high or low

0.45*P(3)

0.55*P(3)

0.45*P(3)

0.55*P(3)

tR(clk)

Rise time, output clock mcspi3_clk

CBP

7.33

7.31

Balls:

AE2 /

AE13

CBP

4.31

4.30

Ball: H26

tF(clk)

Fall time, output clock mcspi3_clk

CBP

6.77

6.71

Balls:

AE2 /

AE13

CBP

4.0

Ball: H26

SM4

td(CLK-SIMO)

Delay time, mcspi3_clk active edge to mcspi3_simo

–2.1

11.3

–5.3

23.6

shifted

SM5

td(CSn-CLK)

Delay time, mcspi3_csi active to

Modes 1

A(4)

– 4.4

A(4)

–

mcspi3_clk first edge

and 3

10.1

Modes 0

B(5)

– 4.4

B(5)

–

and 2

10.1

SM6

td(CLK-CSn)

Delay time, mcspi3_clk last edge to

Modes 1

B(5)

– 4.4

B(5)

–

mcspi3_csi inactive

and 3

10.1

Modes 0

A(4)

– 4.4

A(4)

–

and 2

10.1

SM7

td(csn-simo)

Delay time, mcspi3_csi active edge to

Modes 0

11.3

23.6

mcspi3_simo shifted

and 2

Timing Requirements and Switching Characteristics

227

Submit Documentation Feedback

Product Folder Link(s): AM3715 AM3703

AM3703CUS датащи(PDF) 227 Page - Texas Instruments

AM3703CUS датащи(HTML) 227 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL