AM3703CUS datasheet(196/280 Pages) TI

196 / 280 page

AM3715, AM3703

SPRS616F

– JUNE 2010 – REVISED AUGUST 2011

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(1) The load setting of the IO buffer: LB0 = 1.

Table 6-28. CPI Timing Requirements

—8-Bit SYNC Packed Progressive Mode(4) (5)

NO.

PARAMETER

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

ISP3

1 / tc(pclk)

Frequency (1), input pixel clock cam_pclk

130

MHz

ISP4

tw(pclkH)

Typical pulse duration, input pixel clock

0.5*P(2)

cam_pclk high

ISP4

tw(pclkL)

Typical pulse duration, input pixel clock

0.5*P(2)

cam_pclk low

tdc(pclk)

Duty cycle error, input pixel clock cam_pclk

0.5*P(2) -

3.465

6.93

tJ(pclk)

Cycle jitter(3), input pixel clock cam_pclk

0.0649*P(2)

ISP5

tsu(dV-pclkH)

Setup time, input data cam_d[7:0] valid before

1.08

2.27

input pixel clock cam_pclk rising edge

ISP6

th(pclkH-dV)

Hold time, input data cam_d[7:0] valid after input

1.08

2.27

pixel clock cam_pclk rising edge

ISP7

tsu(dV-vsH)

Setup time, input vertical synchronization

1.08

2.27

cam_vs valid before input pixel clock cam_pclk

rising edge

ISP8

th(pclkH-vsV)

Hold time, input vertical synchronization cam_vs

1.08

2.27

valid after input pixel clock cam_pclk rising edge

ISP9

tsu(dV-hsH)

Setup time, input horizontal synchronization

1.08

2.27

cam_hs valid before input pixel clock cam_pclk

rising edge

ISP10

th(pclkH-hsV)

Hold time, input horizontal synchronization

1.08

2.27

cam_hs valid after input pixel clock cam_pclk

rising edge

ISP11

tsu(dV-hsH)

Setup time, input write enable cam_wen valid

1.08

2.27

before input pixel clock cam_pclk rising edge

ISP12

th(pclkH-hsV)

Hold time, input write enable cam_wen valid

1.08

2.27

after input pixel clock cam_pclk rising edge

(1) Related with the input maximum frequency supported by the ISP module.

(2) P = cam_pclk period in ns

(3) Maximum cycle jitter supported by cam_pclk input clock.

(4) The timing requirements are assured up to the cycle jitter and duty cycle error conditions specified.

(5) See Section 4.3.4, Processor Clocks.

196

Timing Requirements and Switching Characteristics

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