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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM3703CUS датащи(PDF) 170 Page - Texas Instruments |
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AM3703CUS датащи(HTML) 170 Page - Texas Instruments |
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170 / 280 page  AM3715, AM3703 SPRS616F – JUNE 2010 – REVISED AUGUST 2011 www.ti.com Table 6-7. GPMC/NOR Flash Timing Requirements —Asynchronous Mode(7) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX FA5(1) tacc(d) Data access time H(5) H(5) ns FA20(3) tacc1-pgmode(d) Page mode successive data access time P(4) P(4) ns FA21(2) tacc2-pgmode(d) Page mode first data access time H(5) H(5) ns (1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge. FA5 value must be stored inside the AccessTime register bit field. (2) The FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by active functional clock edge. FA21 value must be stored inside the AccessTime register bit field. (3) The FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field. (4) P = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK(6) (5) H = AccessTime * (TimeParaGranularity + 1) * GPMC_FCLK(6) (6) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns. (7) See Section 4.3.4, Processor Clocks. Table 6-8. GPMC/NOR Flash Switching Characteristics —Asynchronous Mode(16) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX tR(d) Rise time, output data gpmc_d[15:0] 2 2 ns tF(d) Fall time, output data gpmc_d[15:0] 2 2 ns FA0 tw(nbeV) Pulse duration, output lower-byte Read N(12) N(12) ns enable/command latch enable Write N(12) N(12) gpmc_nbe0_cle, output upper-byte enable gpmc_nbe1 valid time FA1 tw(ncsV) Pulse duration, output chip select Read A(1) A(1) ns gpmc_ncsx(13) low Write A(1) A(1) FA3 td(ncsV-nadvIV) Delay time, output chip select Read B(2) – 0.2 B(2) + 2.0 B(2) – 0.2 B(2) + 2.6 ns gpmc_ncsx(13) valid to output Write B(2) – 0.2 B(2) + 2.0 B(2) – 0.2 B(2) + 2.6 address valid/address latch enable gpmc_nadv_ale invalid FA4 td(ncsV-noeIV) Delay time, output chip select gpmc_ncsx(13) C(3) – 0.2 C(3) + 2.0 C(3) – 0.2 C(3) + 2.6 ns valid to output enable gpmc_noe invalid (Single read) FA9 td(aV-ncsV) Delay time, output address gpmc_a[27:1] valid J(9) – 0.2 J(9) + 2.0 J(9) – 0.2 J(9) + 2.6 ns to output chip select gpmc_ncsx(13) valid FA10 td(nbeV-ncsV) Delay time, output lower-byte J(9) – 0.2 J(9) + 2.0 J(9) – 0.2 J(9) + 2.6 ns enable/command latch enable gpmc_nbe0_cle, output upper-byte enable gpmc_nbe1 valid to output chip select gpmc_ncsx(13) valid FA12 td(ncsV-nadvV) Delay time, output chip select gpmc_ncsx(13) K(10) – 0.2 K(10) + 2.0 K(10) – 0.2 K(10) + 2.6 ns valid to output address valid/address latch enable gpmc_nadv_ale valid FA13 td(ncsV-noeV) Delay time, output chip select gpmc_ncsx(13) L(11) – 0.2 L(11) + 2.0 L (11) – 0.2 L(11) + 2.6 ns valid to output enable gpmc_noe valid FA14 td(ncsV-iodir) Delay time, output chip select gpmc_ncsx(13) L(11) – 0.2 L(11) + 2.0 L(11) – 0.2 L(11) + 2.6 ns valid to output IO direction control gpmc_io_dir high FA15 td(ncsV-iodir) Delay time, output chip select gpmc_ncsx(13) M(14) – 0.2 M(14) + 2.0 M(14) – 0.2 M(14) + 2.6 ns valid to output IO direction control gpmc_io_dir low 170 Timing Requirements and Switching Characteristics Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 |
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