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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM3703CUS датащи(PDF) 145 Page - Texas Instruments |
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AM3703CUS датащи(HTML) 145 Page - Texas Instruments |
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145 / 280 page  AM3715, AM3703 www.ti.com SPRS616F – JUNE 2010 – REVISED AUGUST 2011 4.3.5 Device Core Clocks Table 4-21 and Table 4-22 show the device core clocks AC performance values. Table 4-21. Device Core Voltages RETENTION OPP50 OPP100 MIN MIN TYP MAX MIN TYP MAX VDD2 (1) (2) (3) (V) 0.8 0.90 0.95 1.00 1.08 1.14 1.20 (1) At ball level. (2) Minimum OPP voltage values defined in this table include any voltage transient. (3) When SmartReflex ™ is not used, these values define the required voltage range. When SmartReflex™ will be used, these voltages are the required voltage range prior to enabling the SmartReflex ™ feature. After calibration, the minimum voltage may be lower than this specification. Table 4-22. Device Core Clocks OPP50 OPP100 Descripti Source Max Ratio Max Ratio Max Ratio Max Ratio Max Ratio Max Ratio on Freq.(MH Freq.(MH Freq.(MH Freq.(MH Freq.(MH Freq.(MH z) z) z) z) z) z) DPLL3 - 800 - 664 - 400 - 800 - 664 - 532 - Locked Frequenc y DPLL3C DPLL3 200 2 *(M2 = 166 2 *(M2 = 200 2 *(M2 = 400 2 *(M2 = 332 2 *(M2 = 266 2 *(M2 = LKOUT_ Locked 2)(1)(2) 1)(1)(2) 1)(1)(2) 1)(1)(2) 1)(1)(2) 1)(1)(2) M2 Frequenc y CORE_C DPLL3C 200 1 166 1 200 1 400 1 332 1 266 1 LK LKOUT_ M2 L3_ICLK CORE_C 100 2(1) 83 2(1) 100 2(1) 200 2(1) 166 2(1) 133 2(1) LK L4_ICLK L3_ICLK 50 2(1) 41.5 2(1) 50 2(1) 100 2(1) 83 2(1) 66.5 2(1) SDRC_C L3_ICLK 100 1 83 1 100 1 200 1 166 1 133 1 LK GPMC_C L3_ICLK 50 2(1) 41.5 2(1) 50 2(1) 100 2(1) 83 2(1) 66.5 2(1) LK (1) This ratio is configurable by software programming. For more information, see the AM/DM37x Multimedia Device Technical Reference Manual (SPRUGN4). (2) The DPLL ratios documented in this table are recommended ratios. Other values may apply. 4.3.6 Graphic Accelerator (SGX) Clocks Table 4-23 and Table 4-24 show the recommended VDD2 (corresponding to vdd_core, Core and SGX voltage at ball level) voltages ranges and the standard graphic accelerator (SGX) clocks speed characteristics vs VDD2. Table 4-23. Graphic Accelerator Voltages OPP 100 (2) MIN TYPICAL MAX VDD2 (1)(3)(4) (V) 1.08 1.14 1.20 (1) At ball level. (2) SGX (Graphic Accelerator) is not available in the OPP50 operating point. (3) When SmartReflex ™ is not used, these values define the required voltage range. When SmartReflex™ will be used, these voltages are the required voltage range prior to enabling the SmartReflex ™ feature. After calibration, the minimum voltage may be lower than this specification. (4) Minimum OPP voltage values defined in this table include any voltage transient. Copyright © 2010–2011, Texas Instruments Incorporated Clock Specifications 145 Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 |
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