AM3703CUS datasheet(144/280 Pages) TI

144 / 280 page

AM3715, AM3703

SPRS616F

– JUNE 2010 – REVISED AUGUST 2011

www.ti.com

Table 4-19. Processor Voltages With SmartReflexTM (continued)

RETENTIO

OPP50

OPP100

OPP130(4)

OPP1G (4) (5)(6)

VDD1(1) (2)

0.8

0.92

0.97

1.02

1.08

1.14

1.2

1.21

1.27

1.33

1.28

1.33

1.38

(3) (V)

(1) At ball level.

(2) These VDD1 (vdd_mpu_iva) values are the required voltage ranges prior to enabling the SmartReflex AVS feature. After calibration, the

minimum voltage may be lower than this specification.

(3) Minimum OPP voltage values defined in this table include any voltage transient.

(4) OPP130 and OPP1G are not available above TJ of 90C.

(5) OPP1G is a high performance operating point which has following requirements:

–

ABB LDO must be set to FBB (Forward Body Bias) mode when switching to this OPP. It requires having a 1

μF capacitor connected

to cap_vdd_bb_mpu_iva.

–

AVS (Adaptive Voltage Scaling) power technique must be used to achieve optimum operating voltage.

(6) Based on DM3730 PCB constraints, the vdd_mpu_iva (VDD1) voltage value calibrated before enabling SmartReflex

™ is recommended

to be 1.38V. Minimum (1.28V) and typical (1.33V) values provided can be achieved only with very good power delivery network design.

For more information on vdd_mpu_iva power delivery network design requirements, see the PCB Design Requirements for

VDD_MPU_IVA Power Distribution Network for TI OMAP3630, AM37xx, and DM37xx Microprocessors (SPRABJ7) application note.

Table 4-20. Processor Clocks

OPP50

OPP100

OPP130

OPP1G (2)

Description

Source Clock

Max

Ratio

Max

Ratio

Max

Ratio

Max

Ratio

Freq.(MHz)

DPLL1

1200

1600

2000

Locked

Frequency

DPLL1CLKO

DPLL1

300

2 *(M2 =

600

2 *(M2 =

800

2 *(M2 =

1000

2 *(M2 =

UT_M2

Locked

2)(1)(4)

1)(1)(4)

Frequency

ARM_FCLK

DPLL1CLKO

300

600

800

1000

UT_M2

(1) This ratio is configurable by software programming. For more information, see the AM/DM37x Multimedia Device Technical Reference

Manual (SPRUGN4).

(2) OPP1G is a high performance operating point which has following requirements:

–

ABB LDO must be set to FBB (Forward Body Bias) mode when switching to this OPP. It requires having a 1

μF capacitor connected

to cap_vdd_bb_mpu_iva.

–

AVS (Adaptive Voltage Scaling) power technique must be used to achieve optimum operating voltage.

(3) For more information about ARM_FCLK and IVA2_CLK processor clocks configuration, see the Power, Reset, and Clock Management /

PRCM Functional Description / PRCM Clock Manager Functional Description / Clock Configurations / Processor Clock Configurations

section or the MPU Subsystem / MPU Subsystem Integration / MPU Subsystem Clock and Reset Distribution / Clock Distribution section

of the AM/DM37x Multimedia Device Technical Reference Manual (SPRUGN4).

(4) The DPLL ratios documented in this table are recommended ratios. Other values may apply.

144

Clock Specifications

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