| поискавой системы для электроныых деталей |
|
AM3703CUS датащи(PDF) 137 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
AM3703CUS датащи(HTML) 137 Page - Texas Instruments |
|
137 / 280 page ![]() SWPS038-009 sys_32k CK0 CK1 CK1 SWPS038-010 sys_altclk ALT0 ALT1 ALT1 AM3715, AM3703 www.ti.com SPRS616F – JUNE 2010 – REVISED AUGUST 2011 (1) In this table, the transition times are calculated for 10%-90% of VDDS. For more information on the corresponding VDDS power supply name, please see the Ball Characteristics table corresponding to your package. The POWER column defines the VDDS power supply for each ball. Figure 4-4. sys_32k Input Clock 4.1.5 sys_altclk CMOS Input Clock Table 4-8 summarizes the electrical characteristics of the sys_altclk input clock. Table 4-8. sys_altclk Input Clock Electrical Characteristics NAME DESCRIPTION MIN TYP MAX UNIT f Frequency, sys_altclk 48 or 54 MHz Ci Input capacitance 1.6 pF Ri Input resistance 3 106 M Ω Table 4-9 details the input requirements of the sys_altclk input clock. Table 4-9. sys_altclk Input Clock Timing Requirements(2) NAME DESCRIPTION MIN TYP MAX UNIT ALT0 1 / tc(altclk) Frequency, sys_altclk 48 or 54 MHz ALT1 tw(altclk) Pulse duration, sys_altclk low or high 0.49 * tc(altclk) 0.51 * tc(altclk) ns tJ(altclk) Peak-to-peak jitter(1), sys_altclk -1% 1% tR(altclk) Rise time, sys_altclk 10 ns tF(altclk) Fall time, sys_altclk 10 ns tJ(altclk) Frequency stability, sys_altclk 50 ppm (1) Peak-to-peak jitter is meant here as follows: – The maximum value is the difference between the longest measured clock period and the expected clock period – The minimum value is the difference between the shortest measured clock period and the expected clock period Maximum and minimum are obtained on a statistical population of 300 period samples and expressed relative to the expected clock period (2) In this table, the transition times are calculated for 10%-90% of VDDS. For more information on the corresponding VDDS power supply name, please see the Ball Characteristics table corresponding to your package. The POWER column defines the VDDS power supply for each ball. Figure 4-5. sys_altclk Input Clock Copyright © 2010–2011, Texas Instruments Incorporated Clock Specifications 137 Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |