AM3703CUS datasheet(133/280 Pages) TI

133 / 280 page

AM3715, AM3703

www.ti.com

SPRS616F

– JUNE 2010 – REVISED AUGUST 2011

The device operation requires the following three input clocks:

•

The sys_32k 32-kHz clock is used for low frequency operation. It supplies the wake-up domain for

operation in lowest power mode (off mode). This clock is provided through the sys_32k pin.

•

The sys_altclk system alternative clock can be used (through the sys_altclk pin) to provide alternative

48 MHz or 54 MHz.

•

The sys_xtalin / sys_xtalout system input clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz) is used to

generate the main source clock of the device. It supplies the DPLLs as well as several other modules.

The system input clock can be connected to either:

– A crystal oscillator clock managed by sys_xtalin and sys_xtalout. In this case, the sys_clkreq is

used as an input (GPIN).

– A CMOS digital clock through the sys_xtalin pin. In this case, the sys_clkreq is used as an output to

request the external system clock.

The device outputs externally two clocks:

•

sys_clkout1 can output the oscillator clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz) at any time. It can be

controlled by software or externally using sys_clkreq control. When the device is in the off state, the

sys_clkreq can be asserted to enable the oscillator and activate the sys_clkout1 without waking up the

device. The off state polarity of sys_clkout1 is programmable.

•

sys_clkout2 can output the oscillator clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz), core_clk (core DPLL

output), 96 MHz or 54 MHz. It can be divided by 2, 4, 8, or 16 and its off state polarity is

programmable. This output is active only when the core power domain is active.

4.1

Input Clock Specifications

4.1.1

Input Clock Requirements

Table 4-1 illustrates the requirements to supply a clock to the device.

Table 4-1. Input Clock Requirements (4)

PAD

CLOCK FREQUENCY

STABILITY

DUTY CYCLE

JITTER

TRANSITION

sys_32k

32.768 kHz

+/- 200 ppm

<10 ns

sys_xtalout

12, 13, 16.8, or 19.2 MHz

Crystal

±50 ppm (±5

sys_xtalin

ppm)(1)

12, 13, 16.8, 19.2, 26, or 38.4 MHz

Square

±50 ppm (±5

45% to 55%

X%(2) *

10 ns

ppm)(1)

tc(xtalin)(3) -

200ps

sys_altclk

48 or 54 MHz

+/-50 ppm

49% to 51%

<1%

10 ns

(1)

± 50 ppm is the clock frequency stability/accuracy and ± 5 ppm takes into account the aging effects.

(2) Depending on the internal system clock divider configuration (PRCM.PRM_CLKSRC_CTRL[7:6], SYSCLKDIV bit field), the sys_xtalin

input clock can be divided by 2 to provide the standard system clock (SYS_CLK) frequencies.

For more information, see the Power, Reset, and Clock Management chapter of the AM/DM37x Multimedia Device Technical Reference

Manual (SPRUGN4). In X%, X represents then the internal system clock divider with following possible values: X = 1 or 2.

(3) tc(xtalin) is the sys_xtalin cycle time of the clock coming to sys_xtalin ball.

(4) In this table, the transition times are calculated for 10%-90% of VDDS. For more information on the corresponding VDDS power supply

name, please see the Ball Characteristics table corresponding to your package. The POWER column defines the VDDS power supply

for each ball.

Clock Specifications

133

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