AM3703CUS datasheet(112/280 Pages) TI

112 / 280 page

AM3715, AM3703

SPRS616F

– JUNE 2010 – REVISED AUGUST 2011

www.ti.com

2.5.8

Power Supplies

Note: For more information, see Power Reset and Clock Management / PRCM Environment and the

Power, Reset, and Clock Management / PRCM Functional Description / PRCM Voltage Management

Functional Description sections of the AM/DM37x Multimedia Device Technical Reference Manual

(literature number SPRUGN4).

Table 2-25. Power Supplies Signals Description(1)

SIGNAL NAME [1]

DESCRIPTION [2]

BALL BOTTOM

BALL TOP

BALL BOTTOM

BALL TOP

BALL BOTTOM

(CBP Pkg.) [4]

(CBP Pkg.) (2)[5]

(CBC Pkg.) [4]

(CBC Pkg.) (2)[5]

(CUS Pkg.) (2) [4]

vdd_mpu_iva

ARM power domain

Y9 / W9 / T9 /

H7/ N7/ U7/ V7/ N8/

W13/ W12/ V13/

R9 / M9 / L9 / J9

G9/ L9/ M9/ W9/ Y9/

V12/ U13/ U12/ T8/

/ Y10 / U10 / T10

M10/ P10/ K11/ U11/

T7/ R8/ R7/ R6/ N8/

/ R10 / N10 /

V11/ Y11/ G12/ D13/

N7/ N6/ M12/ M8/

M10 / L10 / J10 /

U13

M7/ M6/ L12/ L11/

Y11 / W11 / K11

J10/ J9/ H10/ H9/

/ J11 / W12 / K13

G10/ G9/F10

/ Y14 / K14 / J14

/ Y15 / W15 / J15

vdd_core

Core power domain

AC4 / J4 / H4 /

M7/ T7/ Y8/ G11/

T20/ T19/ T18/ T17/

D8 / AE9 / D9 /

Y12/ D15/ M17/ G18/

R19/ R18/ R17/

D15 / Y16 /

H20/ R20/ AC21

M15/ M14/ L15/

AE18 / Y18 /

L14/ K19/ K18/ K17/

W18 / K18 / J18 /

J18/ J17/ H13/ H12/

AE19 / Y19 /

G13/ G12/ F13/ F12

U19 / T19 / N19 /

M19 / J19 / Y20 /

W20 / V20 / U20

/ P20 / N20 / K20

/ J20 / D22 / D23

/ AE24 / M25 /

L25 / E25

cap_vddu_wkup_

Decoupling

AA15

K14

Y12

logic

capacitor for

WKUP/EMU

domains (logic)

vdda_dplls_dll

Input power for the

K15

K13

G18

analog part of the

MPU, CORE

DPLLs, and the DLL

vdda_dac

Video DAC power

V25

AB13

plane

vssa_dac

Video DAC ground

Y26

V24

AB15

plane

vdds

1.8-V power for

AD3 / AD4 / W4 /

G4/ M4/ T4/ Y4/ L7/

A3 / A15 / B5 / F2 /

Y9 / W10 / W9 / V10

standard IOs

AF8 / AE8 /

AC7/ D9/ AE10/ C11/

F21/ L20 / W21

/ V9 / U10 / N19 /

AF16 / AE16 /

J15/ AC15/ A18/ J18/

N18 / N17 / M19 /

AF23 / AE23 /

AC18/ AD20/ E24/

M18 / M17

F25 / F26 / AG27

L24/ T24/ W24/ AC24

/ AB24

vdds_mem

Memory IO power

U1 / J1 / F1 / J2 /

AC5 / P1 / H1 / F23

K8 / K7 / K6 / J8 /

plane

F2 / R4 / B5 / A5

/ E1 / C23 / A4 / A7

J7 / J6 / H15 / G16 /

/ AH6 / B8 / A8 /

/ A10 / A15 / A18

G15 / F16 / F15 /

B12 / A12 / D16 /

E16

C16 / B18 / A18 /

B22 / A22 / G28 /

C28

vdda_dpll_per

Input power for the

AA16

U14

U17

analog part of the

Peripheral DPLLs

vdda_wkup_bg_bb

For wakeup LDO

AA14

W14

AA13

and VDDA (2 LDOs

SRAM and BG)

112

TERMINAL DESCRIPTION

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