MPC5604E datasheet(61/75 Pages) FREESCALE

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Electrical characteristics

MPC5604E Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

3.18.10 Fast ethernet interface

MII signals use CMOS signal levels compatible with devices operating at either 5.0 V or 3.3 V. Signals are not TTL compatible.

They follow the CMOS electrical characteristics.

3.18.10.1 MII receive signal timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)

The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency

requirement. In addition, the system clock frequency must exceed four times the RX_CLK frequency.

Figure 32. MII receive signal timing diagram

3.18.10.2 MII transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)

The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency

requirement. In addition, the system clock frequency must exceed four times the TX_CLK frequency.

The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising or falling edge of

TX_CLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs.

Refer to the Ethernet chapter for details of this option and how to enable it.

Table 34. MII receive signal timing

No.

Parameter

Min

Max

Unit

Rx Clock Period

—

RXD[3:0], RX_DV, RX_ER to RX_CLK setup

5—

RX_CLK to RXD[3:0], RX_DV, RX_ER hold

5—

Rx Clock Duty Cycle

Table 35. MII transmit signal timing1

1 Output pads configured with SRC = 0b11.

No.

Parameter

Min

Max

Unit

TX Clock Period

—

TX_CLK to TXD[3:0], TX_EN, TX_ER invalid

5—

TX_CLK to TXD[3:0], TX_EN, TX_ER valid

—25

TX Clock Duty Cycle

RX_CLK (input)

RXD[3:0] (inputs)

RX_DV

RX_ER

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