AD9512BCPZ datasheet(30/48 Pages) AD

30 / 48 page

AD9512

Rev. A | Page 30 of 48

DIV = 18

Unique Phase Offsets Are Phase = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,

11, 12, 13, 14, 15, 16, 17

Phase offsets may be related to degrees by calculating the phase

step for a particular divide ratio:

Phase Step = 360°/(Divide Ratio) = 360°/DIV

Using some of the same examples,

DIV = 4

Phase Step = 360°/4 = 90°

Unique Phase Offsets in Degrees Are Phase = 0°, 90°,

180°, 270°

DIV = 7

Phase Step = 360°/7 = 51.43°

Unique Phase Offsets in Degrees Are Phase = 0°, 51.43°,

102.86°, 154.29°, 205.71°, 257.15°, 308.57°

DELAY BLOCK

OUT4 (LVDS/CMOS) includes an analog delay element that

can be programmed (Register 34h to Register 36h) to give

variable time delays (ΔT) in the clock signal passing through

that output.

ΔT

FINE DELAY ADJUST

(32 STEPS)

FULL-SCALE: 1ns TO 10ns

OUT4 ONLY

CLOCK INPUT

÷N

∅SELECT

LVDS

CMOS

OUTPUT

DRIVER

Figure 26. Analog Delay (OUT4)

The amount of delay that can be used is determined by the

frequency of the clock being delayed. The amount of delay can

approach one-half cycle of the clock period. For example, for a

10 MHz clock, the delay can extend to the full 10 ns maximum

of which the delay element is capable. However, for a 100 MHz

clock (with 50% duty cycle), the maximum delay is less than

5 ns (or half of the period).

OUT4 allows a full-scale delay in the range 1 ns to 10 ns. The

full-scale delay is selected by choosing a combination of ramp

current and the number of capacitors by writing the appropriate

values into Register 35h. There are 32 fine delay settings for

each full scale, set by Register 36h.

This path adds some jitter greater than that specified for the

nondelay outputs. This means that the delay function should be

used primarily for clocking digital chips, such as FPGA, ASIC,

DUC, and DDC, rather than for data converters. The jitter is

higher for long full scales (~10 ns). This is because the delay

block uses a ramp and trip points to create the variable delay. A

longer ramp means more noise might be introduced.

Calculating the Delay

The following values and equations are used to calculate the

delay of the delay block.

Value of Ramp Current Control Bits (Register 35h or Register 39h

<2:0>) = Iramp_bits

IRAMP (μA) = 200 × (Iramp_bits + 1)

No. of Caps = No. of 0s + 1 in Ramp Control Capacitor

(Register 35h or Register 39h <5:3>), that is, 101 = 1 + 1 = 2;

110 = 2; 100 = 2 + 1 = 3; 001 = 2 + 1 = 3; 111 = 0 + 1 = 1)

Delay_Range (ns) = 200 × [(No. of Caps + 3)/(IRAMP)] × 1.3286

()

1600

0.34

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

RAMP

Caps

No.

Offset

Delay_Full_Scale (ns) = Delay_Range + Offset

Fine_Adj = Value of Delay Fine Adjust (Register 36h or

Delay (ns) = Offset + Delay_Range × Fine_adj × (1/31)

OUTPUTS

The AD9512 offers three different output level choices:

LVPECL, LVDS, and CMOS. OUT0 to OUT2 are LVPECL only.

OUT3 and OUT4 can be selected as either LVDS or CMOS.

Each output can be enabled or turned off as needed to save

power.

The simplified equivalent circuit of the LVPECL outputs is

shown in Figure 27.

3.3V

OUT

OUTB

GND

Figure 27. LVPECL Output Simplified Equivalent Circuit

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