AD9512BCPZ datasheet(14/48 Pages) AD

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AD9512

Rev. A | Page 14 of 48

POWER

Table 9.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER-UP DEFAULT MODE POWER DISSIPATION

550

600

Power-up default state; does not include power

dissipated in output load resistors. No clock.

POWER DISSIPATION

800

All outputs on. Three LVPECL outputs @ 800 MHz,

two CMOS out @ 62 MHz (5 pF load). Does not include

power dissipated in external resistors.

850

All outputs on. Three LVPECL outputs @ 800 MHz,

two CMOS out @ 125 MHz (5 pF load). Does not include

power dissipated in external resistors.

Full Sleep Power-Down

Maximum sleep is entered by setting 0Ah<1:0> = 01b

and 58h<4> = 1b. This powers off all band gap

references. Does not include power dissipated in

terminations.

Power-Down (PDB)

Set FUNCTION pin for PDB operation by setting

58h<6:5> = 11b. Pull PDB low. Does not include

power dissipated in terminations.

POWER DELTA

CLK1, CLK2 Power-Down

Divider, DIV 2 − 32 to Bypass

For each divider.

LVPECL Output Power-Down (PD2, PD3)

For each output. Does not include dissipation

in termination (PD2 only).

LVDS Output Power-Down

110

For each output.

CMOS Output Power-Down (Static)

For each output. Static (no clock).

CMOS Output Power-Down (Dynamic)

115

150

190

For each CMOS output, single-ended. Clocking at

62 MHz with 5 pF load.

CMOS Output Power-Down (Dynamic)

125

165

210

For each CMOS output, single-ended. Clocking at

125 MHz with 5 pF load.

Delay Block Bypass

Vs. delay block operation at 1 ns fs with maximum

delay; output clocking at 25 MHz.

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