AD9512BCPZ datasheet(24/48 Pages) AD

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AD9512

Rev. A | Page 24 of 48

FUNCTIONAL DESCRIPTION

OVERALL

Figure 23 shows a block diagram of the AD9512. The AD9512

accepts inputs on either of two clock inputs (CLK1 or CLK2).

This clock can be divided by any integer value from 1 to 32.

The duty cycle and relative phase of the outputs can be selected.

There are three LVPECL outputs (OUT0, OUT1, OUT2) and

two outputs that can be either LVDS or CMOS level outputs

(OUT3, OUT4). OUT4 can also make use of a variable

delay block.

The AD9512 provides clock distribution function only; there is

no clock clean-up. The jitter of the input clock signal is passed

along directly to the distribution section and can dominate at

the clock outputs.

See Figure 24 for the equivalent circuit of CLK1 and CLK2.

CLOCK INPUT

STAGE

CLK

CLKB

2.5k

Figure 24. CLK1, CLK2 Equivalent Input Circuit

FUNCTION PIN

The FUNCTION pin (Pin 12) has three functions that are

selected by the value in Register 58h<6:5>. There is an internal

30 kΩ pull-down resistor on this pin.

RESETB: 58h<6:5> = 00b (Default)

In its default mode, the FUNCTION pin acts as RESETB, which

generates an asynchronous reset or hard reset when pulled low.

The resulting reset writes the default values into the serial

control port buffer registers as well as loading them into the

chip control registers. The AD9512 immediately resumes

operation according to the default values. When the pin is taken

high again, an asynchronous sync is issued (see the SYNCB:

58h<6:5> = 01b section).

SYNCB: 58h<6:5> = 01b

The FUNCTION pin can be used to cause a synchronization

or alignment of phase among the various clock outputs.

The synchronization applies only to clock outputs that:

•

are not powered down

•

the divider is not masked (no sync = 0)

•

are not bypassed (bypass = 0)

SYNCB is level and rising edge sensitive. When SYNCB is low,

the set of affected outputs are held in a predetermined state,

defined by each divider’s start high bit. On a rising edge, the

dividers begin after a predefined number of fast clock cycles

(fast clock is the selected clock input, CLK1 or CLK2) as

determined by the values in the divider’s phase offset bits.

The SYNCB application of the FUNCTION pin is always active,

regardless of whether the pin is also assigned to perform reset

or power-down. When the SYNCB function is selected, the

FUNCTION pin does not act as either RESETB or PDB.

PDB: 58h<6:5> = 11b

The FUNCTION pin can also be programmed to work as an

asynchronous full power-down, PDB. Even in this full power-

down mode, there is still some residual VS current because

some on-chip references continue to operate. In PDB mode, the

FUNCTION pin is active low. The chip remains in a power-

down state until PDB is returned to logic high. The chip returns

to the settings programmed prior to the power-down.

See the Chip Power-Down or Sleep Mode—PDB section for more

details on what occurs during a PDB initiated power-down.

DSYNC AND DSYNCB PINS

The DSYNC and DSYNCB pins (Pin 1 and Pin 2) are used

when the AD9512 is used in a multichip synchronized

configuration (see the Multichip Synchronization section).

CLOCK INPUTS

Two clock inputs (CLK1, CLK2) are available for use on the

AD9512. CLK1 and CLK2 can accept inputs up to 1600 MHz.

See Figure 24 for the CLK1 and CLK2 equivalent input circuit.

The clock inputs are fully differential and self-biased. The signal

should be ac-coupled using capacitors. If a single-ended input

must be used, this can be accommodated by ac coupling to one

side of the differential input only. The other side of the input

should be bypassed to a quiet ac ground by a capacitor.

The unselected clock input (either CLK1 or CLK2) should be

powered down to eliminate any possibility of unwanted

crosstalk between the selected clock input and the unselected

clock input.

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