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AD9512BCPZ датащи(PDF) 1 Page - Analog Devices |
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AD9512BCPZ датащи(HTML) 1 Page - Analog Devices |
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1 / 48 page ![]() 1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs AD9512 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved. FEATURES Two 1.6 GHz, differential clock inputs 5 programmable dividers, 1 to 32, all integers Phase select for output-to-output coarse delay adjust 3 independent 1.2 GHz LVPECL outputs Additive output jitter 225 fs rms 2 independent 800 MHz/250 MHz LVDS/CMOS clock outputs Additive output jitter 275 fs rms Fine delay adjust on 1 LVDS/CMOS output Serial control port Space-saving 48-lead LFCSP APPLICATIONS Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure FUNCTIONAL BLOCK DIAGRAM SYNC STATUS SYNC STATUS SCLK SDIO SDO CSB SERIAL CONTROL PORT FUNCTION SYNCB, RESETB PDB DSYNC DSYNCB DETECT SYNC VREF RSET AD9512 GND VS CLK1 CLK1B CLK2 CLK2B PROGRAMMABLE DIVIDERS AND PHASE ADJUST OUT0 OUT0B LVPECL /1, /2, /3... /31, /32 OUT1 OUT1B LVPECL /1, /2, /3... /31, /32 OUT2 OUT2B LVPECL /1, /2, /3... /31, /32 OUT3 OUT3B LVDS/CMOS /1, /2, /3... /31, /32 OUT4 OUT4B LVDS/CMOS /1, /2, /3... /31, /32 DELAY ADJUST ΔT Figure 1. GENERAL DESCRIPTION The AD9512 provides a multi-output clock distribution in a design that emphasizes low jitter and low phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements can also benefit from this part. There are five independent clock outputs. Three outputs are LVPECL (1.2 GHz), and two are selectable as either LVDS (800 MHz) or CMOS (250 MHz) levels. Each output has a programmable divider that may be bypassed or set to divide by any integer up to 32. The phase of one clock output relative to another clock output may be varied by means of a divider phase select function that serves as a coarse timing adjustment. One of the LVDS/CMOS outputs features a programmable delay element with a range of up to 10 ns of delay. This fine tuning delay block has 5-bit resolution, giving 32 possible delays from which to choose. The AD9512 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter. The AD9512 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. The temperature range is −40°C to +85°C. |
Аналогичный номер детали - AD9512BCPZ |
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Аналогичное описание - AD9512BCPZ |
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