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LPC810M021FN8 датащи(PDF) 45 Page - NXP Semiconductors

номер детали LPC810M021FN8
подробное описание детали  32-bit ARM Cortex-M0 microcontroller; up to 16 kB flash and 4 kB SRAM
PDF  71 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC810M021FN8 датащи(HTML) 45 Page - NXP Semiconductors

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LPC81xM
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 29 July 2013
45 of 71
NXP Semiconductors
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
12. Dynamic characteristics
12.1 Flash memory
[1]
Number of program/erase cycles.
[2]
Programming times are given for writing 64 bytes to the flash. Tamb <= +85 C. Flash programming with
IAP calls (see LPC800 user manual).
12.2 External clock for the oscillator in slave mode and CLKIN
Remark: The input voltage on the XTAL1/2 pins must be
 1.95 V (see Table 9). For
connecting the oscillator to the XTAL pins, also see Section 14.1.
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Typical ratings are not guaranteed. The values listed are for room temperature (25
C), nominal supply
voltages.
Table 11.
Flash characteristics
Tamb = 40 C to +105 C. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as
specified below.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Nendu
endurance
[1] 10000
100000
-
cycles
tret
retention time
powered
10
20
-
years
unpowered
20
40
-
years
ter
erase time
page or multiple
consecutive pages,
sector or multiple
consecutive
sectors
95
100
105
ms
tprog
programming
time
[2] 0.95
1
1.05
ms
Table 12.
Dynamic characteristic: external clock (XTALIN or CLKIN inputs)
Tamb = 40 C to +105 C; VDD over specified ranges.[1]
Symbol
Parameter
Conditions
Min
Typ[2]
Max
Unit
fosc
oscillator frequency
1
-
25
MHz
Tcy(clk)
clock cycle time
40
-
1000
ns
tCHCX
clock HIGH time
Tcy(clk)  0.4
-
-
ns
tCLCX
clock LOW time
Tcy(clk)  0.4
-
-
ns
tCLCH
clock rise time
-
-
5
ns
tCHCL
clock fall time
-
-
5
ns
Fig 27. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)



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