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LPC810M021FN8 датащи(PDF) 39 Page - NXP Semiconductors |
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LPC810M021FN8 датащи(HTML) 39 Page - NXP Semiconductors |
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39 / 71 page ![]() LPC81xM All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3 — 29 July 2013 39 of 71 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 11.2 CoreMark data WKT not running. Fig 18. Deep power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD Conditions: VDD = 3.3 V; Tamb = 25 C; active mode; all peripherals except one UART and the SCT disabled in the SYSAHBCLKCTRL register; system clock derived from the IRC; system oscillator disabled; internal pull-up resistors enabled; BOD disabled. Measured with Keil uVision v.4.7. Fig 19. Active mode: CoreMark power consumption IDD |
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