MRF49XA-ISLASHT datasheet(64/102 Pages) MICROCHIP

64 / 102 page

MRF49XA

DS70590C-page 64

Preliminary

3.15

Low Duty Cycle Mode

In Low Duty Cycle mode, the receiver periodically

wakes up for a short period and checks for the valid

FSK transmission in progress. The FSK transmission is

detected in the frequency range determined by

CFSREG and the baseband filter bandwidth is

determined by the RXCREG. The on time is

automatically extended until the DQI indicates a good

received signal condition.

The following facts need to be considered while

calculating the duty cycle on-time:

• The crystal oscillator, the synthesizer and the PLL

need time to start (see Table 5-7).

• Depending on the DQTI, the device needs to

receive few valid data bits before the DQI signal

indicates a good signal condition (see

Selecting a short on-time can prevent the crystal

oscillator from starting, or the DQI signal will not go high

even when the received signal has a good quality. The

MRF49XA is normally configured to work in FIFO mode.

However, when the device periodically wakes up from

Sleep mode, it switches to the Receive mode. If valid

FSK data is received, the device sends an interrupt to

the microcontroller and continues filling the RXFIFO. On

completion of transmission, the FIFO is read out

completely and all other interrupts are cleared. The

device then returns to the Low-Power Consumption

mode. Figure 3-13 depicts the Low-Power Duty Cycle

mode sequence.

The low duty cycle is calculated by using the DCMV

(DCSREG<7:1>) and WTMV (WTSREG<7:0>) bits, as

shown in Equation 3-3. The time cycle is determined by

the WTSREG.

EQUATION 3-3:

The registers associated with Low Duty Cycle mode

are:

•STSREG (see Register 2-1)

• GENCREG (see Register 2-2)

• RCXREG (see Register 2-7)

• BBFCREG (see Register 2-8)

• PMCREG (see Register 2-13)

• WTSREG (see Register 2-14)

FIGURE 3-13:

LOW-POWER DUTY CYCLE MODE SEQUENCE

Note: In Duty Cycle mode, the RXCEN bit must

be cleared and the WUTEN bit must be

set in PMCREG.

DC = (DCMV<7:1> x 2 + 1)/WTMV<7:0> x 100%

Transmitter

Receiver

Receiving

DQI

IRO

Microcontroller

Operation

FIFO Read

Packet

Packet A

TWAKE-up

Packet

Start/Send

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