MRF49XA-ISLASHT datasheet(43/102 Pages) MICROCHIP

43 / 102 page

Preliminary

DS70590C-page 43

MRF49XA

3.0

FUNCTIONAL DESCRIPTION

The MRF49XA is a low-power, Zero-IF, multi-channel

FSK transceiver which operates in the 433, 868

and 915 MHz frequency bands. All the RF and

baseband functions and processes are integrated in

the MRF49XA. The device for its operation requires

only a single, 10 MHz crystal as a reference source and

an external, low-cost host microcontroller. The

MRF49XA supports the following functions:

• Reset

• PA and LNA

• Synthesizer (PLL, VCO and Oscillator)

• I/Q Mixers and Demodulators

• BBFs and Amplifiers

• Received Signal Strength Indicator

• Low Battery Detector

• Wake-up Timer/Low Duty Cycle mode

•DQI

The MRF49XA is the best option for FHSS applications

requiring

frequency

agility

meet

Federal

Communications

Commission

(FCC),

Industry

Canada (IC)

European

Telecommunications

Standards

Institute

(ETSI)

requirements.

The

communication link can be created by just using the

MRF49XA along with a low-cost microcontroller. The

device uses the different power-saving modes to reduce

the overall current consumption, and thereby, extends

the battery life of the system or application.

3.1

Reset

The MRF49XA supports four types of Reset:

• Power-on Reset

• Power Glitch Reset

• Software Reset

• Reset Pin

3.1.1

POWER-ON RESET

The MRF49XA has a built-in Power-on Reset circuitry

which automatically resets all control registers when

power is applied. A delay of 100 ms is recommended

after a power-up sequence in order to allow the VDD to

reach the correct voltage level and to get stabilized to

recognize an active-low Reset. In Reset mode, the

device does not accept the control commands through

the SPI.

After power-up, the supply voltage starts to rise

above 0V. The Reset block has an internal ramping

voltage reference level (Reset ramp signal) which rises

at a 100 mV/ms (typical) rate. The device remains in

the Reset state until the voltage difference between the

actual VDD and the internal Reset ramp signal is higher

than

the

Reset

threshold

voltage

level

(typically 600 mV). The device remains in Reset mode

as long as the VDD voltage level is less than 1.6V (typ-

ical), irrespective of the voltage difference between the

VDD and the internal ramp signal. Figure 3-1 graphi-

cally shows the POR example for VDD with respect to

time conditions.

FIGURE 3-1:

POWER-ON RESET EXAMPLE

VDD

1.6V

Reset Threshold

Voltage (600 mV)

Reset Ramp

Line

(100 mV/ms)

Time

The device stays in Reset when VDD < 1.6V

(even if the voltage difference is smaller

than the Reset threshold).

RESET

Output

(Pin 10)

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