MMPF0100NPEP datasheet(104/137 Pages) FREESCALE

104 / 137 page

Analog Integrated Circuit Device Data



104

Freescale Semiconductor

PF0100

Functional Block Requirements and Behaviors

Control Interface I2C Block Description

Coin Cell Specifications

6.5

Control Interface I2C Block Description

The PF0100 contains an I2C interface port which allows access by a processor, or any I2C master, to the register set. Via these

registers the resources of the IC can be controlled. The registers also provide status information about how the IC is operating.

6.5.1

I2C Device ID

I2C interface protocol requires a device ID for addressing the target IC on a multi-device bus. To allow flexibility in addressing for

bus conflict avoidance, fuse programmability is provided to allow configuration for the lower 3 address LSB(s). Refer to One Time

Programmability (OTP) for more details. This product supports 7-bit addressing only; support is not provided for 10-bit or general

call addressing. Note, when the TBB bits for the I2C slave address are written, the next access to the chip, must then use the

new slave address; these bits take affect right away.

6.5.2

I2C Operation

The I2C mode of the interface is implemented generally following the Fast mode definition which supports up to 400 kbits/s

operation (exceptions to the standard are noted to be 7-bit only addressing and no support for General Call addressing.) Timing

diagrams, electrical specifications, and further details can be found in the I2C specification, which is available for download at:

http://www.nxp.com/acrobat_download/literature/9398/39340011.pdf

I2C read operations are also performed in byte increments separated by an ACK. Read operations also begin with the MSB and

each byte will be sent out unless a STOP command or NACK is received prior to completion.

The following examples show how to write and read data to and from the IC. The host initiates and terminates all communication.

The host sends a master command packet after driving the start condition. The device will respond to the host if the master

command packet contains the corresponding slave address. In the following examples, the device is shown always responding

with an ACK to transmissions from the host. If at any time a NACK is received, the host should terminate the current transaction

and retry the transaction.

Figure 27. I2C Write Example

Table 113. Coin Cell Charger Specifications

Parameter

Typ

Unit

Voltage Accuracy

100

Coin Cell Charge Current in On mode ICOINHI

A

Current Accuracy

Device

Address

Packet

Type

START

R / W

Host SDA

Slave SDA

Master Driven Data

( byte

STOP

Host can

also drive

another

Start instead

of Stop

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