DP83848JSQ datasheet(20/80 Pages) TI

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2.5 HALF DUPLEX VS. FULL DUPLEX

The DP83848J supports both half and full duplex operation

at both 10 Mb/s and 100 Mb/s speeds.

Half-duplex relies on the CSMA/CD protocol to handle colli-

sions and network access. In Half-Duplex mode, CRS

responds to both transmit and receive activity in order to

maintain compliance with the IEEE 802.3 specification.

Since the DP83848J is designed to support simultaneous

transmit and receive activity, it is capable of supporting full-

duplex switched applications with a throughput of up to 200

Mb/s per port when operating in 100BASE-TX mode.

Because the CSMA/CD protocol does not apply to full-

duplex operation, the DP83848J disables its own internal

collision sensing and reporting functions and modifies the

behavior of Carrier Sense (CRS) such that it indicates only

receive activity. This allows a full-duplex capable MAC to

operate properly.

All modes of operation (100BASE-TX and 10BASE-T) can

run either half-duplex or full-duplex. Additionally, other than

CRS and Collision reporting, all remaining MII signaling

remains the same regardless of the selected duplex mode.

It is important to understand that while Auto-Negotiation

with the use of Fast Link Pulse code words can interpret

and configure to full-duplex operation, parallel detection

can not recognize the difference between full and half-

duplex from a fixed 10 Mb/s or 100 Mb/s link partner over

twisted pair. As specified in the 802.3u specification, if a

far-end link partner is configured to a forced full duplex

100BASE-TX ability, the parallel detection state machine in

the partner would be unable to detect the full duplex capa-

bility of the far-end link partner. This link segment would

negotiate to a half duplex 100BASE-TX configuration

(same scenario for 10 Mb/s).

2.6 INTERNAL LOOPBACK

The DP83848J includes a Loopback Test mode for facilitat-

ing system diagnostics. The Loopback mode is selected

through bit 14 (Loopback) of the Basic Mode Control Reg-

ister (BMCR). Writing 1 to this bit enables MII transmit data

to be routed to the MII receive outputs. Loopback status

may be checked in bit 3 of the PHY Status Register

(PHYSTS). While in Loopback mode the data will not be

transmitted onto the media. To ensure that the desired

operating mode is maintained, Auto-Negotiation should be

disabled before selecting the Loopback mode.

2.7 BIST

The DP83848J incorporates an internal Built-in Self Test

(BIST) circuit to accommodate in-circuit testing or diagnos-

tics. The BIST circuit can be utilized to test the integrity of

the transmit and receive data paths. BIST testing can be

performed with the part in the internal loopback mode or

externally looped back using a loopback cable fixture.

The BIST is implemented with independent transmit and

receive paths, with the transmit block generating a continu-

ous stream of a pseudo random sequence. The user can

select a 9 bit or 15 bit pseudo random sequence from the

PSR_15 bit in the PHY Control Register (PHYCR). The

received data is compared to the generated pseudo-ran-

dom data by the BIST Linear Feedback Shift Register

(LFSR) to determine the BIST pass/fail status.

The pass/fail status of the BIST is stored in the BIST status

bit in the PHYCR register. The status bit defaults to 0 (BIST

fail) and will transition on a successful comparison. If an

error (mis-compare) occurs, the status bit is latched and is

cleared upon a subsequent write to the Start/Stop bit.

For transmit VOD testing, the Packet BIST Continuous

Mode can be used to allow continuous data transmission,

setting BIST_CONT_MODE, bit 5, of CDCTRL1 (0x1Bh).

The number of BIST errors can be monitored through the

BIST Error Count in the CDCTRL1 (0x1Bh), bits [15:8].

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