DP83848JSQ datasheet(32/80 Pages) TI

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4.3.6 Jabber Function

The jabber function monitors the DP83848J's output and

disables the transmitter if it attempts to transmit a packet of

longer than legal size. A jabber timer monitors the transmit-

ter and disables the transmission if the transmitter is active

for approximately 85 ms.

Once disabled by the Jabber function, the transmitter stays

disabled for the entire time that the ENDEC module's inter-

nal transmit enable is asserted. This signal has to be de-

asserted for approximately 500 ms (the “unjab” time)

before the Jabber function re-enables the transmit outputs.

The Jabber function is only relevant in 10BASE-T mode.

4.3.7 Automatic Link Polarity Detection and Correction

The DP83848J's 10BASE-T transceiver module incorpo-

rates an automatic link polarity detection circuit. When

three consecutive inverted link pulses are received, bad

polarity is reported.

A polarity reversal can be caused by a wiring error at either

end of the cable, usually at the Main Distribution Frame

(MDF) or patch panel in the wiring closet.

The bad polarity condition is latched in the 10BTSCR regis-

ter. The DP83848J's 10BASE-T transceiver module cor-

rects for this error internally and will continue to decode

received data correctly. This eliminates the need to correct

the wiring error immediately.

4.3.8 Transmit and Receive Filtering

External 10BASE-T filters are not required when using the

DP83848J, as the required signal conditioning is integrated

into the device.

Only isolation transformers and impedance matching resis-

tors are required for the 10BASE-T transmit and receive

interface. The internal transmit filtering ensures that all the

harmonics in the transmit signal are attenuated by at least

30 dB.

4.3.9 Transmitter

The encoder begins operation when the Transmit Enable

input (TX_EN) goes high and converts NRZ data to pre-

emphasized Manchester data for the transceiver. For the

duration of TX_EN, the serialized Transmit Data (TXD) is

encoded for the transmit-driver pair (PMD Output Pair).

TXD must be valid on the rising edge of Transmit Clock

(TX_CLK). Transmission ends when TX_EN deasserts.

The last transition is always positive; it occurs at the center

of the bit cell if the last bit is a one, or at the end of the bit

cell if the last bit is a zero.

4.3.10 Receiver

The decoder detects the end of a frame when no additional

mid-bit transitions are detected. Within one and a half bit

times after the last bit, carrier sense is de-asserted.

Receive clock stays active for five more bit times after CRS

goes low, to guarantee the receive timings of the controller.

DP83848JSQ датащи(PDF) 32 Page - Texas Instruments

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