DP83848JSQ datasheet(12/80 Pages) TI

12 / 80 page

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1.4 LED INTERFACE

See Table 3 for LED Mode Selection.

1.5 RESET

1.6 STRAP OPTIONS

DP83848J uses many functional pins as strap options. The

values of these pins are sampled during reset and used to

strap the device into specific modes of operation. The strap

option pin assignments are defined below. The functional

pin name is indicated in parentheses.

A 2.2 k

Ω resistor should be used for pull-down or pull-up to

change the default strap option. If the default option is

required, then there is no need for external pull-up or pull

down resistors. Since these pins may have alternate func-

tions after reset is deasserted, they should not be con-

nected directly to VCC or GND.

Signal Name

Type

Pin #

Description

LED_LINK

S, O, PU

LINK LED: In Mode 1, this pin indicates the status of the LINK.

The LED will be ON when Link is good.

LINK/ACT LED: In Mode 2, this pin indicates transmit and receive

activity in addition to the status of the Link. The LED will be ON

when Link is good. It will blink when the transmitter or receiver is

active.

LED_SPEED

S, O, PU

SPEED LED: This LED is ON when DP83848J is in 100Mb/s and

OFF when DP83848J is in 10Mb/s. Functionality of this LED is in-

dependent of the mode selected.

Signal Name

Type

Pin #

Description

RESET_N

I, PU

RESET: Active Low input that initializes or re-initializes the

DP83848J. Asserting this pin low for at least 1

µs will force a reset

process to occur. All internal registers will re-initialize to their de-

fault states as specified for each bit in the Register Block section.

All strap options are re-initialized as well.

Signal Name

Type

Pin #

Description

PHYAD0 (COL)

PHYAD1 (RXD_0)

PHYAD2 (RXD_1)

PHYAD3 (RXD_2)

PHYAD4 (RXD_3)

S, O, PU

S, O, PD

PHY ADDRESS [4:0]: The DP83848J provides five PHY address

pins, the state of which are latched into the PHYCTRL register at

system Hardware-Reset.

The DP83848J supports PHY Address strapping values 0

(<00000>) through 31 (<11111>). A PHY Address of 0 puts the

part into the MII Isolate Mode. The MII isolate mode must be se-

lected by strapping Phy Address 0; changing to Address 0 by reg-

ister write will not put the Phy in the MII isolate mode. Please refer

to section 2.3 for additional information.

PHYAD0 pin has weak internal pull-up resistor.

PHYAD[4:1] pins have weak internal pull-down resistors.

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