CDCM7005_13 datasheet(28/45 Pages) TI

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T0065-01

ReferenceClock

VCXOClock

Y-Outputdiv4

(90degshift)

Y-Outputdiv8

(90degshift)

90deg

Y-Outputdiv8

90deg

LVCMOSOutputs

LVPECL Outputs

B0058-01

PECL

Input

VCXO_IN

P Divider

÷3

÷4

÷6

÷8

÷16

÷1

÷2

÷4

÷8

P16-Div

CDCM7005

SCAS793E – JUNE 2005 – REVISED FEBRUARY 2013

www.ti.com

Differential LVPECL Outputs and Single-Ended LVCMOS Outputs

The CDCM7005 supports up to 5 × LVPECL outputs or 10 × LVCMOS/LVTTL outputs or any combination of

these. The single-ended LVCMOS outputs are arranged in pairs which mean both outputs of a LVCMOS pair

have the same frequency but can separately be disabled or inverted. The power up output arrangement is five

LVPECL (default setting).

The LVPECL outputs are designed to terminate in to a 50-

Ω load to VCC – 2 V. The LVCMOS outputs supports

the standard LVCMOS load (see Figure 12). The LVPECL and LVCMOS outputs can be enabled (normal

operation) or disabled (3-state).

In addition, the output phase can be shifted by 90 degrees when using the additional div-by-4 or div-by-8 mode

of the P16-Div (see Figure 20). In the default mode (after power up), the div-by-16 mode of the P16-Div is active.

To change it to a 90 degree phase shift, bit 30 or bit 31 of word 1 has to be programmed accordingly. The P 16-

Div has to be selected via the dedicated YxMUX to obtain the 90 degree phase shift. The outputs are switched in

pairs. When selecting the 90 degree phase shift mode, the div-by-16 functions will no longer be available. The 90

degree phase shifted signal is lagging to the non-shifted signal.

Figure 20. 90 Degree Phase Shift Option of P-Divider

The following diagram shows the LVCMOS and LVPECL output signal when 90 degree phase shift is on.

Figure 21. Output Switching Diagram

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