CDCM7005_13 datasheet(18/45 Pages) TI

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CDCM7005

SCAS793E – JUNE 2005 – REVISED FEBRUARY 2013

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PARAMETER MEASUREMENT INFORMATION (continued)

Word 0

PIN AFFECTED

POWER UP

BIT

BIT NAME

DESCRIPTION/FUNCTION

CONDITION

BGA

QFN

Reference Divider M

Reference Divider M Bit 0

Reference Divider M Bit 1

Reference Divider M Bit 2

Reference Divider M Bit 3

Reference Divider M Bit 4

Reference Divider M Bit 5

Reference Divider M Bit 6

Reference Divider M Bit 7

Reference Divider M Bit 8

Reference Divider M Bit 9

VC(X)O Divider N(1)

VCXO Divider N Bit 0

VCXO Divider N Bit 1

VCXO Divider N Bit 2

VCXO Divider N Bit 3

VCXO Divider N Bit 4

VCXO Divider N Bit 5

VCXO Divider N Bit 6

VCXO Divider N Bit 7

VCXO Divider N Bit 8

VCXO Divider N Bit 9

N10

VCXO Divider N Bit 10

N11

VCXO Divider N Bit 11

DLYM0

Progr. Delay M

Reference Phase Delay M Bit 0

DLYM1

Reference Phase Delay M Bit 1

DLYM2

Reference Phase Delay M Bit 2

DLYN0

Progr. Delay N

Feedback Phase Delay N Bit 0

DLYN1

Feedback Phase Delay N Bit 1

DLYN2

Feedback Phase Delay N Bit 2

MANAUT

Manual or Auto Ref.

Manual Reference Clock Selection [0]

A1, B1

36, 37

Automatic Reference Clock Selection [1]

REFDEC

Freq. Detect

Reference Frequency Detection on [0], off [1] (2)

(1)

The frequency applied to the Divider N must be smaller than 300 MHz. A sufficient P Divider must be selected with the FB_MUX to

maintain this criteria.

(2)

If set to low, STATUS_REF will be in normal operation. If set to high, STATUS_REF will be high, even if no valid clock is

detected (<2 MHz). This is useful for reference inputs frequencies less than 2 MHz where the frequency detection circuitry normally

resets the STATUS_REF signal to low.

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