B0064-01

LO1

(PLL)

16-Bit

DAC

16-Bit

DAC

DAC5687

FIR

FIR

DDC

DUC

RF

I

I

Q

Q

14-Bit

ADC

ADS5423

3.84MHz

VCXO

491.52MHz

61.44MHz

491.52MHz

122.88MHz

122.88MHz

Duplexer

LO1

IF1

LNA

90

0

S

PA

FIR

FIR

GC5016

GC5016

THS4509

TRF3750

(PLL)

TRF3702

CDCM7005

CDCM7005

SCAS793E – JUNE 2005 – REVISED FEBRUARY 2013

www.ti.com

In-Band Noise Performance

Table 3.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

–95

dBc/Hz

–162

dBc/Hz

BW = 27 kHz, Feedback Divider = 8 x 282

–218

dBc/Hz

3 mA

(2)

(1)

The synthesizer phase noise floor can be estimated by measuring the in-band noise at the output of the CDCM7005 and subtracting

20log(Feedback Divider) N (in case of CDCM7005 it is the N+P divider). The calculated phase noise floor still based on the PFD update

frequency, in the above specification, is 400 kHz.

(2)

The in-band noise can also be normalized to a comparison frequency of 1 Hz. The resulting phase noise floor is: pnfloor = PNmeasured

where:

pnNfloor = normalized phase noise floor in dBc/Hz

PNmeasured = in-band phase noise measurement in dBc/Hz

20log(N+P) = divider ratio of feedback loop

APPLICATION INFORMATION ON THE CLOCK GENERATION FOR INTERPOLATING DACS

WITH THE CDCM7005

The CDCM7005, with its specified phase noise performance, is an ideal sampling clock generator for high speed

ADCs and DACs. The CDCM7005 is especially of interest for the new high speed DACs, which have integrated

interpolation filter. Such DACs achieve sampling rates up to 500 MSPS. This high data rate can typically not be

supported from the digital side driving the DAC (e.g., DUC, digital up-converter). Therefore, one approach to

interface the DUC to the DAC is the integration of an interpolation filter within the DAC to reduce the data rate at

the digital input of the DAC. In 3G systems, for example, a common sampling rate of a high speed DAC is

491.52 MSPS. With a four times interpolation of the digital data, the required input data rate results into

122.88 MSPS, which can be supported easily from the digital side. The DUC GC5016, which supports up to four

WCDMA carriers, provides a maximum output data rate of 150 MSPS. An example is shown in Figure 26, where

the CDCM7005 supplies the clock signal for the DUC/DDC and ADC/DAC.

Figure 26. CDCM7005 as a Clock Generator for High Speed ADCs and DACs

34

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