CDCM7005_13 datasheet(33/45 Pages) TI

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f − Frequency − Hz

−160

−150

−140

−130

−120

−110

−100

−90

−80

−70

100

100k

10M

10k

G009

CDCM7005 in PLL−Closed Loop

CDCM7005 EVM

REF_IN: AgilentE8257C−61.44MHz

VCXO: Toyocom TCO−2111 245.76MHz

CDCM7005 Out is Y0A: 61.44MHz

Loop bandwidth ~ 30Hz

Date: 30. Mar 2005

Phase-Noise

Analyzer

E5052A

CDCM7005

Ref_Clk

LPF

VCXO

Phase Jitter (rms) − 1kHz − 10MHz

LVPECL

61.44MHz (282fs)

Input−Clk

61.44MHz (769fs)

VXCO

245.76MHz (581fs)

LVCMOS

61.44MHz

(230fs)

CDCM7005

www.ti.com

SCAS793E – JUNE 2005 – REVISED FEBRUARY 2013

Phase Noise Performance

REF_IN PHASE

VCXO PHASE

Yx PHASE NOISE

NOISE

AT 30.72 MHz

PARAMETER(1)

TEST CONDITIONS

UNIT

AT 30.72 MHz

AT 245.76 MHz

LVCMOS

LVPECL

TYP(2)

phn10

Phase noise at 10 Hz

–109

–75

–104

–100

dBc/Hz

phn100

Phase noise at 100 Hz

–125

–97

–116

dBc/Hz

Y = 30.72 MHz; fPFD = 200

phn1k

Phase noise at 1 kHz

–134

–117

–140

dBc/Hz

kHz, Loop BW = 20 Hz,

phn10k

Phase noise at 10 kHz

Feedback Divider = 8 x 128

–136

–138

–153

–152

dBc/Hz

(N x P), fREF_IN = 30.72 MHz,

phn100k

Phase noise at 100 kHz

–138

–148

–156

–153

dBc/Hz

M-Divider = 128, ICP = 2 mA

phn1Mk

Phase noise at 1 MHz

–144

–148

–156

–153

dBc/Hz

phn10M

Phase noise at 10 MHz

–144

–148

–156

–153

dBc/Hz

PLL Stabilization Time

tstabi

PLL stabilization time(3)

Y = 30.72 MHz, fPFD = 200

400

kHz, Loop BW = 20 Hz,

Feedback Divider = 8 x 128

(N x P), fREF_IN = 30.72 MHz,

M-Divider = 128, ICP = 2 mA

(1)

Output phase noise is dependent on the noise of the REF_IN clock and VCXO clock noise floor. The phase noise performance of the

BGA and the QFN package is equal. The phase noise measurements were taken with the CDCM7005 EVM and CDCM7005 SPI default

settings.

(2)

The typical stabilization time is based on the above application example. The stabilization criterion was a stable high level of

PLL_LOCK.

(3)

For further explanations, as well as phase noise/jitter test results using various VCXOs, see application note SCAA067.

Figure 25. Phase Noise (61.44-MHz REF_IN and 61.44-MHz Output Frequency)

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