DSPIC33FJ64GS406 datasheet(115/456 Pages) MICROCHIP

115 / 456 page

 2009-2012 Microchip Technology Inc.

DS70591E-page 115

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

6.0

RESETS

The Reset module combines all Reset sources and

controls the device Master Reset Signal, SYSRST. The

following is a list of device Reset sources:

• POR: Power-on Reset

• BOR: Brown-out Reset

•MCLR: Master Clear Pin Reset

•SWR: Software RESET Instruction

• WDTO: Watchdog Timer Reset

• TRAPR: Trap Conflict Reset

• IOPUWR: Illegal Condition Device Reset

- Illegal Opcode Reset

- Uninitialized W Register Reset

- Security Reset

A simplified block diagram of the Reset module is

shown in Figure 6-1.

Any active source of Reset will make the SYSRST

signal active. On system Reset, some of the registers

associated with the CPU and peripherals are forced to

a known Reset state and some are unaffected.

All types of device Reset sets a corresponding status

bit in the RCON register to indicate the type of Reset

(see Register 6-1).

A POR clears all the bits, except for the POR bit

(RCON<0>), that are set. The user application can set

or clear any bit at any time during code execution. The

RCON bits only serve as status bits. Setting a particular

Reset status bit in software does not cause a device

Reset to occur.

The RCON register also has other bits associated with

the Watchdog Timer and device power-saving states.

The function of these bits is discussed in other sections

of this manual.

FIGURE 6-1:

RESET SYSTEM BLOCK DIAGRAM

Note 1: This data sheet summarizes the features

of the dsPIC33FJ32GS406/606/608/610

and

dsPIC33FJ64GS406/606/608/610

families of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 8. “Reset”

(DS70192) in the “dsPIC33F/PIC24H

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Note:

Refer to the specific peripheral section or

Section 3.0 “CPU” of this data sheet for

Note:

The status bits in the RCON register

should be cleared after they are read so

that the next RCON register value after a

device Reset is meaningful.

MCLR

VDD

Internal

Regulator

BOR

Sleep or Idle

RESET Instruction

WDT

Module

Glitch Filter

Trap Conflict

Illegal Opcode

Uninitialized W Register

SYSRST

VDD Rise

Detect

POR

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