DSPIC33FJ64GS406 datasheet(39/456 Pages) MICROCHIP

39 / 456 page

 2009-2012 Microchip Technology Inc.

DS70591E-page 39

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

3.5

Arithmetic Logic Unit (ALU)

The

dsPIC33FJ32GS406/606/608/610

and

dsPIC33FJ64GS406/606/608/610 ALU is 16 bits wide

and is capable of addition, subtraction, bit shifts and logic

operations. Unless otherwise mentioned, arithmetic

operations are 2’s complement in nature. Depending on

the operation, the ALU can affect the values of the Carry

(C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry

(DC) Status bits in the SR register. The C and DC Status

bits operate as Borrow and Digit Borrow bits, respectively,

for subtraction operations.

The ALU can perform 8-bit or 16-bit operations,

depending on the mode of the instruction that is used.

Data for the ALU operation can come from the W

addressing mode of the instruction. Likewise, output

data from the ALU can be written to the W register array

or a data memory location.

Refer to the “16-bit MCU and DSC Programmer’s

_Reference Manual” (DS70157) for information on the

SR bits affected by each instruction.

The

dsPIC33FJ32GS406/606/608/610

and

dsPIC33FJ64GS406/606/608/610 CPU incorporates

hardware support for both multiplication and division. This

includes a dedicated hardware multiplier and support

hardware for 16-bit divisor division.

3.5.1

MULTIPLIER

Using the high-speed, 17-bit x 17-bit multiplier of the

DSP engine, the ALU supports unsigned, signed or

mixed sign operation in several MCU multiplication

modes:

• 16-bit x 16-bit signed

• 16-bit x 16-bit unsigned

• 16-bit signed x 5-bit (literal) unsigned

• 16-bit unsigned x 16-bit unsigned

• 16-bit unsigned x 5-bit (literal) unsigned

• 16-bit unsigned x 16-bit signed

• 8-bit unsigned x 8-bit unsigned

3.5.2

DIVIDER

The divide block supports 32-bit/16-bit and 16-bit/16-bit

signed and unsigned integer divide operations with the

following data sizes:

• 32-bit signed/16-bit signed divide

• 32-bit unsigned/16-bit unsigned divide

• 16-bit signed/16-bit signed divide

• 16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0 and

the remainder in W1. 16-bit signed and unsigned DIV

instructions can specify any W register for both the 16-bit

divisor (Wn) and any W register (aligned) pair

(W(m + 1):Wm) for the 32-bit dividend. The divide

algorithm takes one cycle per bit of divisor, so both 32-bit/

16-bit and 16-bit/16-bit instructions take the same

number of cycles to execute.

3.6

DSP Engine

The DSP engine consists of a high-speed, 17-bit x

17-bit multiplier, a barrel shifter and a 40-bit adder/

subtracter (with two target accumulators, round and

saturation logic).

The

dsPIC33FJ32GS406/606/608/610

and

dsPIC33FJ64GS406/606/608/610 is a single-cycle

instruction flow architecture; therefore, concurrent

operation of the DSP engine with MCU instruction flow

is not possible. However, some MCU ALU and DSP

engine resources can be used concurrently by the

same instruction (for example, ED, EDAC).

The

DSP

engine

can

also

perform

inherent

accumulator-to-accumulator operations that require no

additional data. These instructions are ADD, SUB and

NEG.

The DSP engine has options selected through bits in

the CPU Core Control register (CORCON), as listed

below:

• Fractional or integer DSP multiply (IF)

• Signed or unsigned DSP multiply (US)

• Conventional or convergent rounding (RND)

• Automatic saturation on/off for ACCA (SATA)

• Automatic saturation on/off for ACCB (SATB)

• Automatic saturation on/off for writes to data

memory (SATDW)

• Accumulator Saturation mode selection

(ACCSAT)

A block diagram of the DSP engine is shown in

Figure 3-3.

TABLE 3-1:

DSP INSTRUCTIONS

SUMMARY

Instruction

Algebraic

Operation

ACC Write

Back

CLR

A = 0

Yes

A = (x – y)2

EDAC

A = A + (x – y)2

MAC

A = A + (x * y)

Yes

MAC

A = A + x2

MOVSAC

No change in A

Yes

MPY

A = x * y

MPY

A = x2

MPY.N

A = – x * y

MSC

A = A – x * y

Yes

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