DSPIC33FJ64GS406 datasheet(33/456 Pages) MICROCHIP

33 / 456 page

 2009-2012 Microchip Technology Inc.

DS70591E-page 33

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

3.0

CPU

The

dsPIC33FJ32GS406/606/608/610

and

dsPIC33FJ64GS406/606/608/610 CPU module has a

16-bit (data) modified Harvard architecture with an

enhanced instruction set, including significant support

for DSP. The CPU has a 24-bit instruction word with a

variable length opcode field. The Program Counter

(PC) is 23 bits wide and addresses up to 4M x 24 bits

of user program memory space. The actual amount of

program memory implemented varies from device to

device. A single-cycle instruction prefetch mechanism

is used to help maintain throughput and provides pre-

dictable execution. All instructions execute in a single

cycle, with the exception of instructions that change the

program flow, the double-word move (MOV.D)

instruction and the table instructions. Overhead-free

program loop constructs are supported using the DO

and REPEAT instructions, both of which are

interruptible at any point.

The

dsPIC33FJ32GS406/606/608/610

and

dsPIC33FJ64GS406/606/608/610 devices have six-

teen, 16-bit working registers in the programmer’s

model. Each of the working registers can serve as a

data, address or address offset register. The sixteenth

working register (W15) operates as a Software Stack

Pointer (SP) for interrupts and calls.

There are two classes of instruction in the

dsPIC33FJ32GS406/606/608/610

and

dsPIC33FJ64GS406/606/608/610 devices: MCU and

DSP. These two instruction classes are seamlessly

integrated into a single CPU. The instruction set

includes many addressing modes and is designed for

optimum C compiler efficiency. For most instructions,

the

dsPIC33FJ32GS406/606/608/610

and

dsPIC33FJ64GS406/606/608/610 is capable of exe-

cuting a data (or program data) memory read, a work-

ing register (data) read, a data memory write and a

program (instruction) memory read per instruction

cycle. As a result, three parameter instructions can be

supported, allowing A + B = C operations to be

executed in a single cycle.

A block diagram of the CPU is shown in Figure 3-1,

and

the

programmer’s

model

for

the

dsPIC33FJ32GS406/606/608/610

and

dsPIC33FJ64GS406/606/608/610

shown

Figure 3-2.

3.1

Data Addressing Overview

The data space can be addressed as 32K words or

64 Kbytes and is split into two blocks, referred to as X

and Y data memory. Each memory block has its own

independent Address Generation Unit (AGU). The

MCU class of instructions operates solely through

the X memory AGU, which accesses the entire

memory map as one linear data space. Certain DSP

instructions operate through the X and Y AGUs to

support dual operand reads, which splits the data

address space into two parts. The X and Y data space

boundary is device-specific.

Overhead-free circular buffers (Modulo Addressing

mode) are supported in both X and Y address spaces.

The Modulo Addressing removes the software

boundary checking overhead for DSP algorithms.

Furthermore, the X AGU circular addressing can be

used with any of the MCU class of instructions. The X

AGU also supports Bit-Reversed Addressing to greatly

simplify input or output data reordering for radix-2 FFT

algorithms.

The upper 32 Kbytes of the data space memory map

can optionally be mapped into program space at any

16K program word boundary defined by the 8-bit

Program Space Visibility Page (PSVPAG) register. The

program-to-data space mapping feature lets any

instruction access program space as if it were data

space.

3.2

DSP Engine Overview

The DSP engine features a high-speed, 17-bit by 17-bit

multiplier, a 40-bit ALU, two 40-bit saturating

accumulators and a 40-bit bidirectional barrel shifter.

The barrel shifter is capable of shifting a 40-bit value up

to 16 bits, right or left, in a single cycle. The DSP

instructions operate

seamlessly with

all

other

instructions and have been designed for optimal real-

time performance. The MAC instruction and other asso-

ciated instructions can concurrently fetch two data

operands from memory while multiplying two W

registers and accumulating and optionally saturating

the result in the same cycle. This instruction

functionality requires that the RAM data space be split

for these instructions and linear for all others. Data

space partitioning is achieved in a transparent and

flexible manner through dedicating certain working

registers to each address space.

Note 1: This data sheet summarizes the features

of the dsPIC33FJ32GS406/606/608/610

and

dsPIC33FJ64GS406/606/608/610

families of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 2. “CPU”

(DS70204) in the “dsPIC33F/PIC24H

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

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